Semiconductor device manufacturing: process – Making device array and selectively interconnecting
Reexamination Certificate
2002-04-11
2003-10-21
Nguyen, Tuan H. (Department: 2813)
Semiconductor device manufacturing: process
Making device array and selectively interconnecting
C438S622000, C438S598000
Reexamination Certificate
active
06635515
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing thereof, in particular, to a multi-layered wiring structure including main power-supply lines, main ground (or grounding) lines, signal lines, and the like.
2. Description of the Related Art
Recently, in the technical field of semiconductor devices, DRAM/logic mixed LSIs have become the focus of attention. Each DRAM/logic mixed LSI provides DRAM functions and logic functions on a single chip.
FIG. 9
is a diagram showing the structure of an example of the DRAM/logic mixed LSI. As shown in the figure, in the DRAM/logic mixed LSI. DRAM area
31
and logic circuit area
32
are provided on a single chip
30
. In addition, a plurality of pads
33
are arranged in a peripheral area of the chip.
FIG. 5
is a partially-enlarged view of the DRAM area
31
.
In the following explanation, the “mask block” corresponds to an area in which a circuit is formed, and a plurality of mask blocks form a “mask block shelf”. Additionally, in
FIG. 5
, each reference numeral in the brackets indicates a specific kind of wiring.
In
FIG. 5
, transistors, capacitors, and the like, arranged in lower layers, are not shown in the DRAM area
1
, and only wiring lines are shown. In this area, a three-layered aluminum (Al) wiring structure is employed, which includes (i) first AL wiring lines
34
(see finely shaded lines) vertically arranged in
FIG. 5
, (ii) second AL wiring lines
35
horizontally arranged in
FIG. 5
, and (iii) third AL wiring lines
36
(see roughly shaded lines) horizontally arranged in FIG.
5
. In the present specification, the first AL wiring lines indicate the AL wiring lines formed in the first layer from the bottom of the three-layered AL wiring structure, the second AL wiring lines indicate the AL wiring lines formed in the second layer from the bottom of the three-layered AL wiring structure, and the third AL wiring lines indicate the AL wiring lines formed in the third layer from the bottom of the three-layered AL wiring structure.
In the illustrated DRAM/logic mixed LSI, each first AL wiring line
34
is used as (i) a line for vertically connecting a P-channel transistor and an N-channel transistor in a mask block, (ii) a power-supply line (called a “VDD line”, hereinafter)
41
or a ground (or grounding or earth) line (called a “GND line”, hereinafter)
42
in a mask block, (iii) a signal line for connecting vertically adjacent mask block shelves, or the like.
Each second AL wiring line
35
is used as a VDD line
38
or a GND line
39
in a mask block shelf, a wide area signal line (called a “bus line”, hereinafter)
40
, or the like.
Each third AL wiring line
36
is used as a main VDD line
43
or a main GND line
44
which has a larger width and which is used in common between mask block shelves, or the like. Generally, in conventional DRAMs, the main VDD lines, main GND lines, and the like are formed using the second AL wiring lines. However, in the no DRAM/logic mixed LSI, the above-explained structure is often employed as required by the design of relevant logic circuits.
FIG. 6
is an enlarged view of an area (see the circled area indicated by reference symbol D in
FIG. 5
) where the first AL wiring line
34
, the second AL wiring line
35
, and the third AL wiring line
36
are connected so as to provide a GND line arrangement.
FIG. 7
is a cross-sectional view along line B—B in FIG.
6
. As shown in
FIG. 6
, enlarged portion
42
a
(enlarged in the width direction) is formed in the GND line
42
formed by the first AL wiring line
34
, and first through holes
45
and second through holes
46
, having the same diameter (or width), are formed in a manner such that they are vertically aligned. Between the first through holes
45
and the second through holes
46
, a GND line
39
formed by the second AL wiring line
35
is provided, and a main GND line
44
formed by the third AL wiring line
36
is provided above the second through holes
46
.
FIG. 7
is a cross-sectional view of the above area shown in
FIG. 6
, and
FIG. 7
also shows a portion including a transistor. As shown in
FIG. 7
, transistor
50
is formed on silicon substrate
47
, which comprises a gate electrode
48
, and N
+
diffusion layers
49
a
and
49
b
functioning as source and drain electrodes. The first AL wiring lines
34
formed on the first inter-layer insulating film
51
are respectively connected to N
+
diffusion layers
49
a
and
49
b
via the first contacts
52
. On one of the GND lines
42
formed by the first AL wiring line, the fist through holes
45
, passing through the second inter-layer insulating film
53
, are formed. The GND line
42
formed by the first AL wiring line
34
and the GND line
39
formed by the second AL wiring line
35
are connected via the first conductors
55
in the first through holes
45
.
In addition, above the GND line
39
formed by the second AL wiring line
35
, the second through holes
46
are formed, which pass through the third inter-layer insulating film
56
. The GND line
39
formed by the second AL wiring line
35
and the main GND line
44
formed by the third AL wiring line
36
are connected via the second conductors
58
in the second through holes
46
. Therefore, the earth voltage of the main GND line
44
formed by the third AL wiring line
36
is supplied via the GND line
39
formed by the second AL wiring line
35
to the GND line
42
formed by the first AL wiring line
34
. Here, the arrangement including the VDD lines is not shown, but has a similar structure.
The conventional DRAM/logic mixed LSI having the above-explained structure has the following problems.
FIG. 7
shows the portion where the first, second, and third AL wiring lines are connected so as to provide a GND line arrangement, while
FIG. 8
shows a sectional view (along line E—E in
FIG. 6
) showing a portion where the bus line
40
are provided. In the DRAM/logic mixed LSI, the bus line
40
is formed by the second AL wiring line
35
, and the main GND line
44
is formed by the third AL wiring line
36
. Therefore, as shown in
FIG. 8
, the main GND line
44
having a larger width is positioned above the bus line
40
, while below the bus line
40
, the first AL wiring line
34
is positioned. Accordingly, the bus line is positioned between the first and third AL wiring lines via each inter-layer insulating film; thus, capacity (or capacitance) is generated at either side of the bus line, thereby increasing the parasitic capacitance of the bus line.
Depending on the increase of the parasitic capacitance of the bus line, the delay of the signal passing through the relevant bus line is also increased, so that the timing between the above signal and the other signals becomes out of order, which may cause various kinds of operational errors. Therefore, in order to adjust the signal timing between a plurality of bus lines, lines for adjusting the wiring capacity are provided in advance, the mask pattern is changed according to need, and the line for adjusting the wiring capacity is connected to any bus line, so that the wiring capacity is adjusted between the bus lines. In the above DRAM/logic mixed LSI, such lines for adjusting the wiring capacity are formed in advance by using the second AL wiring line, that is, formed in the same layer as that of each bus line, and the formed lines function as AL master slice signal lines used for changing the pattern.
In the design and experimental manufacture of a device, it is important to quickly complete the debugging process of the characteristics of the product. However, in the above DRAM/logic mixed LSI, the AL master slice signal lines for changing the pattern are formed in the second layer of the three-layer wiring structure; thus, the mask pattern in the second AL wiring lines is changed, and after the relevant mask is formed, the manufacturing processes (carried out on the wafer) before the patterning of the second AL wiring lines are started again. Therefore, t
Michael Best & Friedrich LLC
NEC Corporation
Nguyen Tuan H.
LandOfFree
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