Method of manufacturing a semiconductor device having narrow cop

Details Method of manufacturing a semiconductor device having narrow cop Method of manufacturing a semiconductor device having narrow cop

1984-10-04

1986-03-11

Hearn, Brian E.

Metal working

Method of mechanical manufacture

Assembling or joining

29577C, 29578, 29591, 357 24, 156653, H01L 2190

Patent

active

045744688

ABSTRACT:
A method of manufacturing a semiconductor device, for example an SPS memory having narrow coplanar silicon electrodes. The electrodes are formed by etching grooves or slots (10) having a width in the submicron range into a polycrystalline silicon layer (3), the slot width being defined by the oxidized edge (6) of a silicon auxiliary layer (5). The electrodes are alternately covered by silicon oxide and by a layer comprising silicon nitride. According to the invention, the electrodes formed covered by silicon oxide (3B, 13B) are first interconnected pairwise, whereupon they are separated from each other in a separate etching step and are provided with self-aligned contact windows (15). Thus, the very narrow electrodes can be contacted without technological problems and memory cells of very small dimensions can be obtained.

REFERENCES:
patent: 4449287 (1984-05-01), Maas et al.

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