Fishing – trapping – and vermin destroying
Patent
1991-04-30
1994-04-05
Chaudhuri, Olik
Fishing, trapping, and vermin destroying
437193, 437228, 437238, H01L 21265
Patent
active
053004442
ABSTRACT:
A semiconductor memory device comprising memory cells having stacked capacitors has a stacked structure formed by the selective removal of a polycrystalline silicon film (15; 20) and a silicon oxide film (18a; 18), employing the same mask (14). A field effect transistor connected to a stacked capacitor has a gate electrode (20) formed of the above described polycrystalline silicon film. This polycrystalline silicon film (20) is formed on the major surface of a semiconductor substrate. The above described silicon oxide film (18) as an upper layer insulating film formed on the gate electrode (20) has a residual stress not more than 10.sup.9 dyn/cm.sup.2. No notches occur in the polycrystalline silicon film (20) in the process of selectively removing the polycrystalline silicon film (15) and the silicon oxide film (18a) deposited thereon, employing the same mask (14), thereby not decreasing the operation speed of the field effect transistor having the gate electrode (20) formed of the polycrystalline silicon film.
REFERENCES:
patent: 4394401 (1983-07-01), Shioya et al.
patent: 4455737 (1984-06-01), Godejahn, Jr.
patent: 4546535 (1985-10-01), Shepard
patent: 4584205 (1986-04-01), Chen et al.
patent: 4754313 (1988-06-01), Takemae et al.
patent: 4789644 (1988-12-01), Meda
patent: 4845047 (1989-07-01), Holloway et al.
patent: 4851361 (1989-07-01), Schumann et al.
patent: 4851370 (1989-07-01), Doklan et al.
patent: 4855801 (1989-08-01), Kuesters
patent: 4905064 (1990-02-01), Yabu et al.
patent: 5028566 (1991-07-01), Lagendijk
patent: 5087951 (1992-02-01), Chang et al.
Su, "Low Temperature Silicon Processing Techniques for VLSIC Fab." in Solid State Technology, Mar. 1981, pp. 72-82.
H. L. Peek, "The Characterization and Technology of Deposited Oxides for EEPROM" Edited by Vermeij et al., 1983, New York, pp. 261-265.
Sze, "Deposition Process in VLSI Technology" second edition 1983, Graw Hill Series in EE, NY, pp. 235-261.
S. M. Sze, VLSI Technology, 1983, p. 119.
Sze, "VLSI Technology" second edition 1988, McGraw Hill Book Company, pp. 248-265, New York.
Peng et al., "Optimization of Submicron Polysilicon Etching and the Effect of Organic and Inorganic Masks, and Their Aspect Ratios," J. Electrochem. Soc.: Solid-State Science and Technology, vol. 133, No. 7, (Jul. 1986), pp. 1479-1484.
Levin et al., "Oxide Isolation for Double-Polysilicon VLSI Devices," J. Electrochem. Soc.: Solid-State Science and Technology, vol. 130, No. 9 (Sep. 1983), pp. 1894-1897.
Smolinsky et al., "Measurements of Temperature Dependent Stress of Silicon Oxide Films Prepared by a Variety of CVD Methods," J. Electrochem. Soc.: Solid-State Science and Technology, vol. 132, No. 4 (Apr. 1985), pp. 950-954.
Chin et al., "Plasma TEOS Process for Interlayer Dielectric Applications," Solid State Technology, Apr. 1988, pp. 119-122.
Peccoud et al., "New trends and limits in plasma etching," J. Phys. D.: Appl. Phys., vol. 20 (1987), pp. 851-857.
Cardinaud et al., "Contamination of Silicon Surfaces Exposed to CHF.sub.3 Plasmas; An XPS Study of the Film and the Film-Surface Interface," Journal of the Electrochemical Society, Jun. 1988, pp. 1472-1477.
Engelhardt et al., "A New CBrF.sub.3 Process for Etching Tapered Trenches in Silicon," Journal of the Electrochemical Society, Aug. 1987, pp. 1985-1988.
Gualandris et al., "Some etch properties of doped and undoped silicon oxide films formed by atmospheric pressure and plasma-activated chemical vapor distillation," J. Vac. Sci. Technol. B3 (6), Nov./Dec. 1985, pp. 1604-1608.
Sakai et al., "Tolpography Modeling in Dry Etching Processes," J. Electrochem. Soc.: Solid-State Science and Technology, vol. 131, No. 3 (Mar. 1984), pp. 627-632.
Koyanagi et al., "Novel High Density, Stacked Capacitor MOS RAM," Central Research Laboratory, Hitachi LTD., IEDM Digest of Technical Papers, 1978, pp. 348-351.
Genjou Hideki
Hachisuka Atsushi
Matsukawa Takayuki
Nagatomo Masao
Ogoh Ikuo
Chaudhuri Olik
Mitsubishi Denki & Kabushiki Kaisha
Tsai H. Jey
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