Method of manufacturing a semiconductor device having a dummy ce

Details Method of manufacturing a semiconductor device having a dummy ce Method of manufacturing a semiconductor device having a dummy ce

1995-07-14

1997-06-24

Tsai, Jey

Semiconductor device manufacturing: process

Making device array and selectively interconnecting

Rendering selected devices operable or inoperable

438241, H01L 2170, H01L 2700

Patent

active

056416997

ABSTRACT:
In a semiconductor device, an outer peripheral part of an integrated circuit region separated by an insulation part is defined as a dummy cell region and a center part except the outer peripheral part of the integrated circuit region is defined as an active cell region. Memory cells such as DRAM, SRAM, EEPROM, mask ROM are formed in the active cell region. In the integrated circuit region, plural cell forming regions are provided which are respectively defined by an isolation. Active cells each having a field effect semiconductor element are provided in a region included in the active cell region of each cell forming region. Dummy cells each having an element inoperable as an semiconductor element are provided in a region included in the dummy cell region of each cell forming region. At last one of dummy cells is made to be a P-N lacking dummy cell having a semiconductor element in construction including at least a gate and excluding at least one of P-N junction parts from the same construction as the field effect semiconductor element in the active cells. All dummy cells may be the P-N lacking dummy cells. Thereby, insulation defects through the P-N lacking dummy cell due to disturbance of gate pattern and the like in the dummy cell region is prevented.

REFERENCES:
patent: 4264965 (1981-04-01), Onishi
patent: 4612565 (1986-09-01), Shimizu et al.
patent: 4830977 (1989-05-01), Katto et al.

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