Semiconductor device manufacturing: process – With measuring or testing
Reexamination Certificate
2001-09-26
2003-08-05
Fabmy, Wael (Department: 2814)
Semiconductor device manufacturing: process
With measuring or testing
C438S017000
Reexamination Certificate
active
06602725
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a manufacturing method thereof, in which a monitor pattern is provided for accurate measurement of the thickness of an interlayer insulating film.
2. Background Art
In recent years, silicon integrated circuit devices have been miniaturized in a vertical direction less than in a horizontal direction. For this reason, recent semiconductor devices have become more three-dimensional, and an absolute step becomes larger in the scale of a chip or wafer.
With a view to miniaturizing semiconductor memory while ensuring an increase in the capacitance of a capacitor, memory cells become more three-dimensional, and a large step arises between the memory cells and peripheral circuits. In an integrated logic circuit, wiring patterns are multilayered in order to improve the performance and speed of the logic circuit. As a result, a step is formed between an area where wiring patterns are densely formed and an area where wiring patterns are sparsely formed. Such a step poses a serious problem in transferring a pattern on a substrate.
With regard to the pattern transfer technique, an increase in resolving power imposes a problem of a shallow depth of focus. The depth of focus becomes significantly small as a result of an increase in the aperture of a lens or of a reduction in the wavelength of light. Such a reduction in the depth of focus presents a problem in miniaturizing a semiconductor device as the device becomes more three-dimensional. If an attempt is made to miniaturize the semiconductor device to a much greater extent, a planarization technique for smoothing the absolute step must be adopted into the pattern transfer process in order to enable a pattern to be transferred at a small depth of focus.
Conventionally-employed techniques for smoothing an inter-layer insulation film, such as SOG or BPSG reflow techniques, are for local smoothing, e.g. , an area of micrometers. For this reason, it is impossible to smooth the absolute steps in the scale of a chip or wafer using these techniques. For the time being, it is only possible to use a chemical mechanical polishing method.
To respond to such a demand, a chemical mechanical polishing method (hereinafter often referred to as a CMP or a CMP method ) such as that shown in
FIG. 7
has already been proposed [see Japanese Patent Publication (Tokkyo Koho) No. 5-30052 or Japanese Patent Application Laid-open (Kokai) No. 7-285050].
In
FIG. 7
, reference numeral
111
designates a rotary table (or platen);
112
designates an abrasive cloth;
113
designates a semiconductor wafer having an insulating film formed thereon;
114
designates packing material;
115
designates an abrasive head; and
116
designates an abrasive agent. The abrasive cloth
112
is attached to the rotary table
111
with an adhesive, and the rotary table
111
rotates around a spindle. The packing material
114
is fixed on the abrasive head
115
with an adhesive. The semiconductor wafer
113
having an insulating film is attached to the packing material
114
with the surface of the insulating film facing down by means of vacuum chucking or surface tension of water.
An actual abrasive method will be described by reference to FIG.
7
. In
FIG. 7
, the rotary table
111
is rotated around the spindle, and the abrasive head
115
is also rotated around another spindle. While the abrasive agent
116
is applied to the surface of the abrasive cloth
112
at a given flow rate, the abrasive head
115
is pressed against the abrasive cloth
112
at a given pressure, whereby the surface of the insulating film of the semiconductor wafer
113
is abraded.
FIGS. 8A
to
8
F are illustrations for explaining an example of an actual abrasive process which uses such a CMP method. In
FIGS. 8A
to
8
F, reference numeral
21
designates a silicon substrate;
22
designates an oxide film;
23
designates a first diffused layer;
24
designates a nitrided film;
25
designates a silicon electrode;
26
designates a second diffused layer;
27
designates an insulating film provided below a wiring pattern (hereinafter simply referred to as an insulating film );
28
designates a first metal wiring layer;
29
designates an interlayer insulating film; and
30
designates a second metal wiring layer.
The nitrided film mask
24
is formed on the silicon substrate
21
, and the oxide film
22
and the first diffused layer
23
are formed on the nitrided film mask (FIG.
8
A). The silicon electrode
25
and the second diffused layer
26
are formed on the oxide film
22
(FIG.
8
B). After formation of the insulating film-
27
, a contact hole is formed in the insulating film, and the first metal wiring layer
28
is formed on the insulating film
27
(FIG.
8
C). The interlayer insulating film
29
is formed on the first metal wiring layer
28
and the insulating film
27
(FIG.
8
D). Subsequently, the interlayer insulating film
29
is smoothed through use of the foregoing chemical mechanical polishing method (FIG.
8
E). After a through hole has been formed in the interlayer insulating film, the second metal wiring layer
30
is formed on the interlayer insulating film (FIG.
8
F).
At this time, in terms of product control, the thickness of a film, the amount of abrasion, and the thickness of a film after abrasion must be controlled by measuring the thickness of the interlayer insulating film
29
from above an aluminum wiring pattern.
To this end, a pattern for the purpose of measuring film thickness is formed in a scribe line, and the thickness of a film before and after abrasion is usually controlled through use of the thus-formed pattern.
FIG. 9
is a schematic representation showing an example of layout of a monitor pattern for the purpose of measuring film thickness conventionally formed in a semiconductor wafer. In the drawing, reference numeral
1
designates a semiconductor wafer;
3
designates a scribe line area (hereinafter also referred to as a scribe line, as required);
5
designates a chip formed on the semiconductor wafer
1
; and
9
designates a monitor pattern for the purpose of measuring film thickness formed in the scribe line
3
.
Under the foregoing chemical mechanical abrasive method, the flatness of a film is dependent on a pattern formed thereon. In short, it takes a longer time to smooth steps as the pattern becomes broader and denser. In the case of a semiconductor device—in which patterns are densely formed over a broad area within a chip—such as DRAM or a DRAM-mixed logic IC, a result which is obtained by measurement of thickness of the film using the film-thickness monitor pattern
9
of the scribe line does not necessarily match the thickness of a circuit portion of the film actually measured. Such a discrepancy in thickness poses a problem of deterioration of reliability of CMP process control.
SUMMARY OF THE INVENTION
The present invention has been contrived to solve the foregoing problem in the background art, and the object of the present invention is to provide a structure and a manufacturing method of a semiconductor device which enables accurate measurement of thickness of a polished and smoothed insulating film.
According to one aspect of the present invention, a semiconductor device comprises a semiconductor wafer partitioned into a plurality of chip regions by a scribe line area. At least one device formation region is provided in the chip region. A device pattern is provided in the device formation region. A monitor pattern is provided in the chip region. An interlayer insulating film is provided on the semiconductor wafer so as to cover the device pattern and the monitor pattern. Thus, the thickness of the interlayer insulating film may be measured on the monitor pattern.
In the semiconductor device, the monitor pattern is provided preferably in the device formation region or adjoining the device forming region.
In another aspect, in the semiconductor device, a memory cell pattern is provided in the device forming area.
I
Chibahara Hiroyuki
Iwasaki Masanobu
Sakai Yuichi
Suda Kakutaro
Fabmy Wael
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
Pham Hoai
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