Semiconductor device manufacturing: process – Making device or circuit responsive to nonelectrical signal – Responsive to electromagnetic radiation
Reexamination Certificate
2001-07-30
2003-05-13
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Making device or circuit responsive to nonelectrical signal
Responsive to electromagnetic radiation
C438S595000
Reexamination Certificate
active
06562651
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to method of manufacturing a semiconductor device, and more particularly to method of manufacturing a semiconductor device having contact pads.
This application is a counterpart of Korean Patent Application No. 2001-1615, filed on Jan. 11, 2001, the disclosure of which is incorporated by reference herein in its entirety and for all purposes.
BACKGROUND OF THE INVENTION
The need to reduce the size of semiconductor chips has driven the effort to decrease line width and spacing at the integrated circuit (IC) level. In order to increase the alignment margin in photolithography process for forming contact holes which penetrate a given region between the lines, a self-aligned contact (SAC) technique has been developed and used. Also, in the case of a highly integrated semiconductor device, a technique of decreasing aspect ratio of contact holes by disposing contact pads between a lower and a upper conductive layer is widely-used.
FIG. 1
to
FIG. 5
are flow diagrams showing the process steps of a conventional method of forming contact pads in self-aligned contact holes.
Referring now to
FIG. 1
, a metal-oxide-semi-conductor (MOS) structure includes an insulated gate pattern
8
formed over the semiconductor substrate
1
. The gate pattern
8
, which is insulated from the substrate
1
by a gate insulating layer
3
, includes gate electrodes
5
, and a capping layer pattern
7
. Adjacent the gate pattern
8
, sidewall spacers
9
are formed.
FIG. 2
shows, a conformal etch stop layer
11
formed followed by formation of a first interlayer insulating layer
13
over the surface of the substrate on which the sidewall spacers
9
. The etch stop layer
11
is formed of a layer of material, which has an etch selectivity relative to the first interlayer insulating layer
13
. For example, the etch stop layer
11
is formed of a silicon nitride layer and the first interlayer insulating layer
13
is formed of a silicon oxide layer. On the first interlayer insulating layer
13
, a hard mask layer is formed. The hard mask layer is formed of a layer of material which has an etch selectivity relative to the first interlayer insulating layer
13
and the etch stop layer
11
. Illustratively, the hard mask layer is a polysilicon layer. The hard mask layer is patterned to form a hard mask
15
. The patterning of the hard mask layer exposes a particular region of the first interlayer insulating layer
13
. The hard mask
15
defines position of contact holes formed in a subsequent process.
FIG. 3
shows that the first interlayer insulating layer
13
and the etch stop layer
11
are etched to form self-aligned contact holes
17
. Formation of contact holes
17
exposes a surface of the substrate
1
under openings or gaps of the gate patterns
8
. In the surface of the substrate
1
, etch damage may be generated. The etch damage may cause deterioration of contact resistance characteristic between the surface of the substrate
1
and contact pads formed in a subsequent process. As such, an etch damage layer may be removed by carrying out a pre-cleaning process that includes use of a dry and a wet cleaning process against the substrate on which the self-aligned contact holes
17
are formed. The wet cleaning process is carried out by using an oxide etchant in order to remove native oxides remained on the surface of the substrate
1
exposed through the self-aligned contact holes
17
. Thus, when the pre-cleaning process is finished, undercuts
19
are formed under edges of openings or gaps of the hard mask
15
.
As shown in
FIG. 4
, a doped polysilicon layer
21
, which fills the self-aligned contact holes
17
, is formed over the substrate over which the pre-cleaning process is carried out. At this time, voids
23
can be formed in the doped polysilicon layer
21
positioned in the self-aligned contact holes
17
.
The voids
23
are formed due to the undercuts
19
.
As shown in
FIG. 5
, the doped polysilicon layer
21
, the hard mask
15
and the first interlayer insulating layer
13
are etched to form contact pads
21
a
in the self-aligned contact holes
17
by a planarization process. Because of the voids
23
, recesses are formed in center portions of the contact pads
21
a
. Thereafter, a second interlayer insulating layer
25
is formed over the substrate on which the contact pads
21
a
are formed. The second interlayer insulating layer
25
is patterned to form openings
27
. To wit, bit line contact holes or storage node contact holes are formed which expose the contact pads
21
a.
It is difficult to completely remove portions
25
a
of the second interlayer insulating layer
25
deposited in the recesses even though the second interlayer insulating layer
25
is over-etched. Therefore, exposed area of the contact pads
21
a
is decreased, thereby increasing contact resistance between the contact pads
21
a
and a conductive layer formed in the openings
27
in a subsequent process.
What is needed, therefore is a method of fabricating contact pads with improved contact resistance that overcomes the shortcomings of the related art described above.
SUMMARY OF THE INVENTION
According to an illustrative embodiment of the present invention, a method of manufacturing a semiconductor device having contact pads includes conformably forming a first conductive layer in self-aligned contact holes, and then transforming profile of sidewalls of the first conductive layer to have a positive slope by anisotropically etching the first conductive layer. A second conductive layer is formed over substrate on which the first conductive layer is anisotropically etched.
Advantageously, by virtue of the illustrative process voids are not formed in the self-aligned contact holes.
REFERENCES:
patent: 5275972 (1994-01-01), Ogawa et al.
patent: 6245625 (2001-06-01), Gau
patent: 6268292 (2001-07-01), Violette et al.
patent: 6376924 (2002-04-01), Tomita et al.
patent: 6387759 (2002-05-01), Park et al.
Chi Kyeong-Koo
Chung Seung-pil
Jeon Jung-Sik
Dang Phuc T.
Nelms David
Volentine & Francos, PLLC
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