Semiconductor device manufacturing: process – Making device array and selectively interconnecting – Using structure alterable to nonconductive state
Utility Patent
1998-08-18
2001-01-02
Zarabian, Amir (Department: 2824)
Semiconductor device manufacturing: process
Making device array and selectively interconnecting
Using structure alterable to nonconductive state
C438S705000, C438S601000
Utility Patent
active
06168977
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method-of manufacturing a semiconductor device having fuse conductive patterns for repairing electrical deficiencies of the semiconductor device. The present invention also relates to a method of inspecting whether or not a fuse part of the semiconductor device is normally formed in its structure.
2. Description of the Related Art
An electrical deficiency of a semiconductor device (LSI) is difficult to find in the course of production process. It is usually discovered in an electrical test performed after the production process, that is, the manufacturing process of the semiconductor device is complete. Some semiconductor device has fuse conductive patterns to repair the electrical deficiencies after the electrical test. The electrical deficiencies discovered in the test can be repaired by cutting the fuse conductive patterns with laser beam (referred to as “fuse blow” hereinafter).
A fuse part includes a fuse conductive patterns, a fuse cover layer formed on the conductive patterns and a fuse opening formed on the fuse cover layer. The fuse opening is formed to etch an interlayer insulation layer on the fuse cover layer. At fuse part of good quality, where fuse structure is normal, the fuse blow can be normally performed and the fuse conductive pattern is cut off. The fuse blow is one of the important factors for achieving good production quantity or production yield of the LSI having the fuse conductive pattern. Following conditions must be satisfied in order for the correct fuse blow.
(1) A fuse conductive pattern should be completely covered by the fuse cover layer. If the fuse conductive pattern is exposed during production process or is left being exposed to the air, a resistance value of the fuse conductive pattern is changed. If the resistance value is changed, the LSI may get unstable in its circuits operation, because a fuse conductive pattern with no fuse blow performed may operate in a similar way as a fuse conductive pattern with the fuse blow performed.
(2) A thickness of the fuse cover layer should be thin enough everywhere in a wafer so that the fuse conductive pattern can be cut by laser beam during the fuse blow.
(3) Where the interlayer insulation layer formed on the fuse cover layer includes an insulation layer having a water absorption property, such layer should be completely removed inside the fuse opening hole. If the insulation layer is exposed on the bottom of the fuse opening hole, the LSI conductive pattern may get corrosion.
For the purpose of etching the interlayer insulation layer formed on the fuse cover layer, an etching condition should be set that a selective ratio of an etching speed of the fuse cover layer to an etching speed of the interlayer insulation layer should be lower than 1. However, since the fuse cover layer is made of insulation material, the selective ratio of the fuse cover layer to the interlayer insulation layer may be 1 or more (which means etching speed of the fuse cover layer is faster than that of the interlayer insulation layer). Also, according to the prior art, the interlayer insulation layer is difficult to be formed as having a uniform layer thickness everywhere in a wafer. Accordingly, the fuse cover layer is overly etched at an area of a wafer, where the interlayer insulation layer is too thin, and the interlayer insulation layer is left without being etched out at an area of a wafer, where the interlayer insulation layer is too thick. Thus as the fuse cover layer on the fuse circuits can not be left, having a uniform thickness everywhere in a wafer so as not to meet the conditions described in the above (1) and (2). Where the conditions (1) and (2) are not satisfied, the fuse blow cannot be performed correctly and the LSI has a malfunction. Also the condition described in the above (3) can sometimes not be complied with due to the remainder of the interlayer insulation layer.
In addition, there is no suitable method of inspecting a thickness of the remainder of the fuse cover layer formed within the fuse opening hole except for a breakdown inspection. That is, a thickness of the remainder of fuse cover layer inside the fuse opening area can not be directly measured. Accordingly, a dummy fuse cover layer is formed in a monitor area and it is etched together with the fuse cover layer inside the fuse opening hole. Then, a thickness of the remainder of the dummy fuse cover layer is measured with an optical measurement equipment. A thickness of the remainder of the fuse cover layer formed inside the fuse opening hole is presumed from a measured thickness obtained from the above measurement in order to judge whether the fuse part is normally formed.
SUMMARY OF THE INVENTION
It is an object of this invention to provide a method of manufacturing a semiconductor device having a fuse conductive pattern, enabling
(1) an insulation layer having a uniform thickness to be formed on the fuse conductive pattern, and
(2) an LSI conductive pattern formed around a fuse opening hole to be prevented from corrosion.
It is another object of this invention to provide a method of inspecting a semiconductor device having a fuse conductive pattern, enabling whether or not a fuse part is normally formed to be easily judged.
In order to accomplish the foregoing objects, the present invention comprises providing a silicon substrate; forming a fuse conductive pattern on the silicon substrate; forming a first insulation layer on the fuse conductive pattern and the silicon substrate, the first insulation layer having a first etching speed; forming a stopper pattern on a first region of the first insulation layer to cover the fuse conductive pattern, the stopper pattern having a second etching speed; forming a second insulating layer on the stopper pattern and the first insulation layer, the second insulation layer having a third etching speed; etching a second region of the second insulating layer to form an opening wherein the second region is within the first region and an etching condition is set that the first etching speed is higher than the second etching speed so that the stopper pattern is exposed on a bottom of the opening; and etching the exposed stopper pattern with an etching condition that the second etching speed is faster than the third etching speed so that the exposed stopper pattern is removed and the first insulation layer remains on the fuse conductive pattern.
REFERENCES:
patent: 5235205 (1993-08-01), Lippitt, III
patent: 5965927 (1999-10-01), Lee et al.
patent: 6011286 (2000-01-01), Wu
Jones Volentine, L.L.C.
OKI Electric Industry Co., Ltd.
Smith Bradley K
Zarabian Amir
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