Fishing – trapping – and vermin destroying
Patent
1992-12-29
1994-01-18
Hearn, Brian E.
Fishing, trapping, and vermin destroying
437 6, 437 41, 437 50, 437 57, H01L 21265
Patent
active
052799778
ABSTRACT:
On the p.sup.- substrate, the n.sup.- epitaxial layer is surrounded and isolated by the p well. In the surface of the n.sup.- epitaxial layer, there is provided the p floating region in the vicinity of the p well, on which the sense electrode is provided. The insulation film and the conductive film are formed on the n.sup.- epitaxial layer between the p well and the p floating region to overlap them. The conductive film and the p floating region serve as a composite field plate, which makes it hard that the surface electric field distribution is influenced by the state of electric charge in the surface and relieves the surface electric field by expanding the depletion layer, which extends from the pn junction between the n.sup.- epitaxial layer and the p well into the n.sup.- epitaxial layer in current blocking state, toward the center of the n.sup.- epitaxial layer. The potential of the p floating region is determined by capacity coupling in the current blocking state and thus the sense voltage characteristics through the sense electrode can be smooth.
REFERENCES:
patent: 3463977 (1969-08-01), Grove et al.
patent: 4567502 (1986-01-01), Nakagawa et al.
patent: 4713681 (1987-12-01), Beasom
patent: 4721986 (1988-01-01), Kinzer
patent: 4922327 (1990-05-01), Mena et al.
patent: 4933740 (1990-06-01), Baliga et al.
patent: 4942440 (1990-07-01), Baliga et al.
patent: 4963951 (1990-10-01), Adler et al.
patent: 4992844 (1991-02-01), Yakushiji
S.N. 08/027,939 Mar. 1993 Yamaguchi 257/213.
Wildi et al., "500V BiMOS Technology and its applications", IEEE, pp. 37-41, 1985.
Becke, "Approaches to Isolation in High Voltage Integrated Circuits", Int. Elec. Dev. Meeting, Washington, D.C., Dec. 1-4, 1985, pp. 724-727.
Akio Nakagawa et al., "High Voltage Low On-Resistance VDMOS FET", Japanese Journal of Applied Physics Suppl. vol. 21, 1982, pp. 97-101.
1985 IEEE, Eric J. Wildi et al, 500V BIMOS Technology and Its Applications pp. 37-41.
Fukunaga Masanori
Kida Takeshi
Majumdar Gourab
Satsuma Kazumasa
Terashima Tomohide
Hearn Brian E.
Mitsubishi Denki & Kabushiki Kaisha
Nguyen Tuan
LandOfFree
Method of manufacturing a semiconductor device for extracting a does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of manufacturing a semiconductor device for extracting a , we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of manufacturing a semiconductor device for extracting a will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1136015