Fishing – trapping – and vermin destroying
Patent
1993-07-22
1995-02-07
Hearn, Brian E.
Fishing, trapping, and vermin destroying
437203, 437913, 148DIG126, H01L 21265
Patent
active
053875281
ABSTRACT:
A semiconductor body (3) has a first region (4) of one conductivity type adjacent one major surface (5). A first masking layer (6) comprising at least one first mask window (6a) spaced from a second mask window (6b) is defined on the surface (5). Opposite conductivity type impurities are then introduced through the first masking layer (6) and a second masking layer (8) which is selectively removable with respect to the first masking layer (6) is subsequently provided on the first masking layer and patterned to leave a mask area (8a) covering the first mask window (6a). The semiconductor body (3) is then etched through the second mask window (6b) to define a recess (9) extending into the first region (4) while leaving the introduced impurities beneath the masked first mask window (6a) to form a relatively highly doped second region (7). The first and second masking layers (6 and 8) are removed and an insulated gate structure (10) is provided by defining a gate insulating layer (10a) on the recess walls (9a) and providing a gate conductive region (10b) on the insulating layer (10a). A relatively lowly doped third region (11) of the opposite conductivity type is provided to extend between the relatively highly doped second region (7) and the recess (9) to provide a conduction channel area (11a) adjacent the insulated gate structure (10). A fourth region (12) is provided to form a potential barrier (12a) with the relatively lowly doped third region (11) so that the conduction channel area (11a) provides a conductive path between the fourth and first regions (12 and 4).
REFERENCES:
patent: 4573066 (1986-02-01), Whight
patent: 4707719 (1987-11-01), Whight
patent: 4774560 (1988-09-01), Coe
patent: 4830981 (1989-05-01), Baglee et al.
patent: 4904613 (1990-02-01), Coe et al.
patent: 4914058 (1990-04-01), Blanchard
patent: 4920064 (1990-04-01), Whight
patent: 4983535 (1991-01-01), Blanchard
patent: 5072266 (1991-12-01), Bulucea et al.
patent: 5160491 (1992-11-01), Mori
patent: 5242845 (1993-09-01), Baba et al.
Siemens Forschungs und Entwicklungsberichte BD 9 (1980) at pp. 190-194; "SIPMOS Technology, an Example of VLSI Precision Realized with Standard LSI for Power Transistor".
Goodyear Andrew L.
Hutchings Keith M.
Warwick Andrew M.
Biren Steven R.
Hearn Brian E.
Trinh Michael
U.S. Philips Corporation
LandOfFree
Method of manufacturing a semiconductor device comprising an ins does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of manufacturing a semiconductor device comprising an ins, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of manufacturing a semiconductor device comprising an ins will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1109929