Method of manufacturing a semiconductor device by implanting ion

Metal treatment – Compositions – Heat treating

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148187, 357 91, 357 13, 357 20, H01L 21265

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041040856

ABSTRACT:
Method of manufacturing a semiconductor device, in particular a capacitance diode, a zener diode or an avalanche diode, by using only one masking step. According to the invention, a first masking layer, for example a silicon oxide layer, is provided on a substrate of one conductivity type the etching rate of which at the surface is increased, for example, by an argon bombardment. A second masking layer is provided on the first masking layer and a window is etched therein. Via said window a first zone preferably of the same conductivity type as the substrate is implanted while using the second masking layer as a mask. The first masking layer is etched via the same window so that a bevelled edge is formed. By ion implantation via the window and a part of the bevelled edge, a second zone is formed which forms a p-n junction preferably with the first zone and the substrate.

REFERENCES:
patent: 3617391 (1973-11-01), Lepselter
patent: 3666548 (1972-05-01), Brack et al.
patent: 3697829 (1972-10-01), Huth et al.
patent: 3769109 (1973-10-01), MacRae et al.
M. Bakowski et al., "--Bevel Angle--on Breakdown Voltage of--Diffused PN Junctions" Sol. St. Electr. 18 (1975) 651.
P. Zandveld, "--Propert's of Ion-Implanted PN-Junctions in Si", Sol. St. Elec. 19 (1976) 659.
J.M. Fairfield et al., "Contacting Buried Ion Implanted Layers", IBM Tech. Discl. Bull. 13, 10/1970; 1052.

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