Semiconductor device manufacturing: process – Chemical etching – Combined with the removal of material by nonchemical means
Reexamination Certificate
2001-04-03
2002-12-17
Powell, William A. (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Combined with the removal of material by nonchemical means
C257S753000, C257S759000, C438S723000, C438S740000
Reexamination Certificate
active
06495466
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a technique for the manufacture of a semiconductor device, and, more particularly, to a multilevel interconnection structure which is fabricated using the so-called damascene method and a technique which is effective when applied to a semiconductor device having such a multilevel interconnection structure.
As semiconductor devices tend to have a higher performance and a more miniaturized structure, a multilevel metallization technique has become necessary for their fabrication. For forming metallization layers in a semiconductor integrated circuit device, there is a known process of forming, over an interlayer insulating film, a thin film of a refractory metal, such as an aluminum (Al) alloy or tungsten; forming thereover a resist pattern having the same shape as that of the interconnection pattern by photolithography; and, then etching the thin film using this resist pattern as a mask, thereby forming interconnection patterns. However, this process using an aluminum allo or the like has the inherent problem that there is a marked increase in the wiring resistance owing to the miniaturization of interconnections, which increases the wiring delay, thereby lowering the performance of the semiconductor device. Particularly, in a high-performance logic LSI (Large Scale Integrated Circuit), it causes a serious problem which represents a performance inhibiting factor.
A method (so-called damascene method) of forming an interconnection pattern in a groove, which has been made in an interlayer insulating film, by embedding therein an interconnection metal having copper (Cu) as a main conductor and removing an unnecessary portion of the metal outside the groove by CMP (Chemical Mechanical Polishing) is therefore under investigation.
SUMMARY OF THE INVENTION
As an interlayer insulating film wherein a groove to be embedded with a copper interconnection is to be formed, a structure is proposed which has an etching stopper film and a TEOS oxide film stacked one after another in this order. The TEOS oxide film is formed by plasma CVD (Chemical Vapor Deposition) using a TEOS (Tetra Ethyl Ortho Silicate: Si (OC
2
H
5
)) gas and an ozone (O
3
) gas. As the etching stopper film, a silicon nitride film is usually employed, when the interlayer insulating film is made of a TEOS oxide film.
Since the dielectric constant of the silicon nitride film is as high as about 7, disposal of it in the interlayer insulating film, however, increases the dielectric constant of the whole interlayer insulating film. This problem causes a rise in the capacitance between interconnections, leading to deterioration in the acting speed of operation of the semiconductor device or an increase in the power consumption. A technique for incorporating a silicon nitride film in the interlayer insulating film is described, for example, in U.S. Pat. No. 6,051,508.
Employment of a material which has a relatively low dielectric constant of about 2 to 3 and a high etching selectivity relative to the TEOS oxide film has been investigated; and, an organic SOG (Spin On Glass) film which is relatively stable to heat and has high resistance to humidity is regarded as promising for use as a material constituting the interlayer insulating film.
As a result of an investigation of a method of multilevel metallization in an interlayer insulating film, which has an organic SOG film as an etching stopper film, by the damascene method, the present inventors have found that such method involves a problem as described below.
When a groove pattern is formed by successively processing the TEOS oxide film and organic SOG film, using with the patterned resist film as a mask, and then the resist film is removed by oxygen plasma, an —OH group is formed in the organic SOG film and it roughens the film quality. Formation of the —OH group is accompanied by an increase in the water content in the organic SOG film, and when heat is applied thereto, film shrinkage due to a dehydration condensation reaction occurs, resulting in the appearance of cracks in the organic SOG film.
An object of the present invention is to provide a technique which is capable of improving the reliability of the damascene interconnection.
Another object of the present invention is to provide a technique which is capable of reducing the capacitance between interconnections, thereby improving the performance of the semiconductor device.
The above-described objects, further objects and novel features of the present invention will be apparent from the description herein and the accompanied drawings.
Among the aspects and features disclosed in the present application, typical ones will next be summarized below:
(1) A method of manufacturing a semiconductor device comprises the steps of: (a) successively depositing, over a base having a plug or interconnection formed thereon, a first insulation film, a second insulation film having a lower etching resistance than the first insulating film, and a hard mask; (b) forming thereover a resist pattern; (c) etching the hard mask in the presence of the resist pattern, thereby transferring the pattern of the resist pattern to the hard mask; (d) removing the resist pattern; (e) etching the second insulating film in the presence of the hard mask, thereby selectively transferring the pattern of the hard mask to the second insulating film; and (f) etching the first insulating film in the presence of the hard mask, thereby transferring the pattern of the hard mask to the first insulating film, wherein the first insulating film is an organic-functional-group-containing insulating film having a lower dielectric constant than a silicon oxide film and the second insulating film has a lower dielectric constant than a silicon nitride film.
(2) A method of manufacturing a semiconductor device comprises the steps of: (a) successively depositing, over a base having a plug or interconnection formed thereon, a first insulating film, a second insulating film having a lower etching resistance than the first insulating film, and a hard mask; (b) forming thereover a resist pattern; (c) etching the hard mask in the presence of the resist pattern, thereby transferring the pattern of the resist pattern to the hard mask; (d) removing the resist pattern; (e) etching the second insulating film in the presence of the hard mask, thereby selectively transferring the pattern of the hard mask to the second insulating film; and (f) etching the first insulating film in the presence of the hard mask, thereby transferring the pattern of the hard mask to the first insulating film, wherein the first insulating film is an organic-functional-group-containing insulating film having a lower dielectric constant than a silicon oxide film; the second insulating film has a lower dielectric constant than a silicon nitride film; and the first insulating film, the second insulating film and the hard mask are deposited to have thicknesses of about 50 to 200 nm, about 200 to 2000 nm, and about 50 to 200 nm, respectively.
(3) A method of manufacturing a semiconductor device comprises the steps of: (a) successively depositing, over a base having a plug or interconnection formed thereon, a first insulating film, a second insulating film having a lower etching resistance than the first insulating film, and a hard mask; (b) forming thereover a resist pattern; (c) etching the hard mask in the presence of the resist pattern, thereby transferring the pattern of the resist pattern to the hard mask; (d) removing the resist pattern; (e) etching the second insulating film in the presence of the hard mask, thereby selectively transferring the pattern of the hard mask to the second insulating film; and (f) etching the first insulating film in the presence of the hard mask, thereby transferring the pattern of the hard mask to the first insulating film, wherein the first insulating film is an organic-functional-group-containing insulating film having a lower dielectric constant than a silicon oxide film; the second insulating film has a lower dielect
Funatsu Keisuke
Hara Kazusato
Imai Toshinori
Noguchi Junji
Ohashi Naohumi
Antonelli Terry Stout & Kraus LLP
Hitachi , Ltd.
Powell William A.
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