Semiconductor device manufacturing: process – Chemical etching – Combined with the removal of material by nonchemical means
Reexamination Certificate
2002-07-01
2004-09-07
Vinh, Lan (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Combined with the removal of material by nonchemical means
C438S692000, C438S693000, C438S700000, C438S745000
Reexamination Certificate
active
06787471
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a method of manufacturing a semiconductor device and, more particularly, to a manufacturing method suitable for forming efficiently a wiring pattern or an isolating trench which partitions an active region in a semiconductor substrate.
2. Description of the Background Art
Semiconductor integrated circuits (ICs) are required to be able to completely independently control individual devices. For this reason, in the fabrication of semiconductor ICs there is a need to form the structure having element isolating regions which prevent electrical interference among a plurality of devices. For example, trench isolation and localized oxidation of silicon (LOCOS) are widely known as the method for forming the aforementioned element isolating regions.
The trench isolation method is one which forms a trench in a semiconductor substrate and then fills the trench with an insulator to form an isolating region. According to the trench isolation method, a bird's beak, which will occur in the LOCOS method, will rarely occur. To accurately form the isolating region, it is undesirable for a bird's beak to occur. In this regard, the trench isolation method is an isolating-region formation method indispensable for advancing miniaturization of semiconductor ICs.
The tolerance for accuracy of lithography and etching that are performed in the semiconductor IC manufacturing process becomes less as miniaturization of semiconductor ICs advances. To enhance lithography accuracy and etching accuracy, it is important to ensure the planarization of a semiconductor IC in the manufacturing process. For this reason, in the process of forming an isolating region by the trench isolation method, chemical mechanical polishing (CMP) has been used extensively for planarizing a semiconductor IC favorably.
FIGS. 15A through 19B
are sectional views for explaining the contents of a former trench isolation method that is performed in the IC manufacturing process.
FIGS. 15A
,
16
A,
17
A,
18
A and
19
A are sectional views showing a section where two isolating regions are provided adjacently to each other, while
FIGS. 15B
,
16
B,
17
B,
18
B and
19
B are show sectional views showing a section where a relatively large active region is formed near an isolating region.
In the former trench isolation method, as illustrated in
FIGS. 15A and 15B
, a silicon dioxide (SiO
2
) film
12
and a silicon nitride (SiN) film
13
are formed in this order on a silicon substrate
10
. Then, a layer of resist (not shown) is formed on the SiN film
13
by a photo-lithographic process. The resist is formed so as to have openings on the regions where isolating regions are to be formed and cover active regions where elements are to be formed. After formation of the above-mentioned resist, etching is performed while the resist is used as a mask, whereby an isolating trench for partitioning an active region is formed.
After the formation of the isolating trench, silicon dioxide (SiO
2
) is deposited on the silicon substrate
10
through use of a chemical vapor deposition (CVD) method, as illustrated in
FIGS. 16A and 16B
. As a result, the isolating trench is filled by a SiO
2
film
14
. Then, CMP is performed to remove the protruding portion of the SiO
2
film
14
. During the CMP process, the SiN film
13
serves as a stopper film. As a result, SiO
2
remains only within the isolating trench, as illustrated in
FIGS. 17A and 17B
.
Next, as illustrated in
FIGS. 18A and 18B
, the SiN film
13
is removed through use of a phosphoric acid heated to a predetermined temperature. Finally, as illustrated in
FIGS. 19A and 19B
, the SiO
2
layer
12
is removed through use of a fluoric acid. The aforementioned steps results in a formation of a trench-shaped isolating region.
In the former trench isolation method, CMP for polishing the protruding portion of the SiO
2
film
14
is performed by employing slurry containing SiO
2
. However, the polishing selectivity ratio of a SiO
2
film and a SiN film implemented by the slurry containing SiO
2
is about 3:1. To polish efficiently only the SiO
2
film
14
by the CMP so as to ensure a desirable polished quality, it is advantageous that the above-mentioned selectivity ratio has a greater value. It is also desirable that the above-mentioned selectivity ratio have a great value in order to favorably flatten the surface of the silicon substrate
10
by execution of the CMP.
To manufacturing semiconductor ICs having stable quality at a high yield, it is important to fabricate isolating regions efficiently and accurately. Further, to fabricate isolating regions efficiently and accurately, it is important to ensure a desired polished quality stably by CMP as well as to ensure a favorable flatness by CMP. For these points, in the former trench isolation method, there is yet room for improvement which enhances a yield of semiconductor ICs having stable quality.
SUMMARY OF THE INVENTION
The present invention has been conceived to solve the previously-mentioned problems, and a general object of the present invention is to provide a novel and useful method of manufacturing a semiconductor device.
A more specific object of the present invention is to provide a manufacturing method for semiconductor devices in which CMP is executed under a condition suitable to ensures a desired polished quality and a favorable flatness, thereby enabling a high yield manufacturing of semiconductor devices having stable characteristics.
The above object of the present invention is achieved by a method of manufacturing a semiconductor device including the steps below. The method includes a step for forming a silicon nitride film on a semiconductor substrate. The silicon nitride film serves as a polishing stopper film The method also includes a step for etching the silicon nitride film and the semiconductor substrate in a region to form an isolating trench which partitions an active region. The method further includes a step for depositing a silicon oxide film on the semiconductor substrate so that the isolating trench is filled with the silicon oxide film and a surface level difference is formed thereon. The single silicon oxide film is polished to reduce the surface level difference, by employing a first slurry suitable for polishing a silicon oxide film and also suitable for reducing the surface level difference or reducing a slope of the surface level difference. The silicon oxide film is further polished until the silicon nitride film is exposed, by employing a second slurry which contains cerium dioxide, after the surface level difference has been reduced.
The above object of the present invention is achieved by a method of manufacturing a semiconductor device including the steps below. The method includes a step for forming a silicon nitride film on a semiconductor substrate. The silicon nitride film serves as a polishing stopper film. The method also includes a step for etching the silicon nitride film and the semiconductor substrate in a region to form an isolating trench which partitions an active region. The method further includes a step for depositing a silicon oxide film on the semiconductor substrate so that the isolating trench is filled with the silicon oxide film and a surface level difference is formed thereon. A surface depression in the silicon oxide film is filled with a flattening material to reduce the surface level difference. The silicon oxide film is polished until the silicon nitride film is exposed, by employing a slurry which contains cerium dioxide, after the surface level difference has been reduced.
The above object of the present invention is achieved by a method of manufacturing a semiconductor device including the steps below. The method includes a step for forming a silicon nitride film on a semiconductor substrate. The silicon nitride film serves as a polishing stopper film. The method also includes a step for etching the silicon nitride film and the semiconductor substrate in a region
McDermott Will & Emery LLP
Renesas Technology Corp.
Vinh Lan
LandOfFree
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