Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
2000-03-20
2001-10-16
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
C438S758000, C438S778000, C438S710000, C438S401000, C438S246000, C438S692000
Reexamination Certificate
active
06303466
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to a method for manufacturing a semiconductor device especially directed to formation of a trench.
To maximize the capacity obtained from a limited area of a semiconductor memory device, for example, a trench capacitor is used, and it is necessary to make a deep trench.
Such a deep trench is usually made by an etching process. As the hard mask for this etching, a CVD SiO
2
film obtained by decomposing TEOS (tetraethoxysilane, Si(OC
2
H
5
)
4
) by low-pressure CVD (LP-CVD) has often been used conventionally.
However, this film involves a problem that it is difficult to remove it evenly when it is etched-off by dry etching or other method after a trench is made. This invites the problem that a difference in level is formed on a silicon oxide film after the dry etching for removing the CVD SiO
2
film has been performed and this level difference adversely affects subsequent steps of the manufacturing process. Moreover, in case of TEOS, there is another problem that the CVD SiO
2
film cannot be etched off soon after etching for forming trench.
On the other hand, there are doped oxides like BSG, BPSG, PSG as materials that have been treated similarly to insulating materials of the group of CVD-SiO
2
referred to above. These BSG, BPSG and PSG exhibit a higher etching speed during wet etching as compared with a TEOS film, for example, and they are advantageous because they can be readily removed after being used as a hard mask.
FIGS. 1A through 1D
show cross-sectional views in different steps in a process of making a trench by using BSG as the doped oxide.
First formed on a silicon semiconductor substrate
11
is a BSG film by CVD, for example. Further coated on the BSG film is a resist
13
by spin coating, for example (FIG.
1
A).
After that, exposure and development are conducted by using an exposure mask corresponding to a desired pattern, and the resist
13
is patterned (FIG.
1
B).
Then, by using the patterned resist
13
′ as an etching mask, the BSG film
12
is etched (FIG.
1
C).
Subsequently, the resist
13
′ is removed, and by using the etched BSG film
12
′ as a hard mask, silicon
11
is etched to form a deep trench (FIG.
1
D).
After the trench is made, the BSG film
12
′ is removed.
However, in the case where a doped oxide like BSG, BPSG, PSG, or the like, as the hard mask material, the etched shape is more liable to vary than using other CVD SiO
2
film as the hard mask.
It is believed that this problem occurs because, due to the natures of BSG, BPSG and PSG readily absorbing moisture, the moisture contained in the BSG, BPSG or PSG film is released into the chamber atmosphere during processing, and this invites fluctuation of the etching characteristics.
Since the quantity of moisture absorbed in BSG, BPSG or PSG varies with the atmosphere in which the sample is exposed, it is impossible to prevent that the processing characteristics delicately change with the exposing condition and other factors.
Therefore, when a BSG, BPSG or PSG film is used, there is a problem that the etching conditions have to be changed unlike the cases using a SiO
2
film.
SUMMARY OF THE INVENTION
It is therefore an object of the invention to provide a method for manufacturing a semiconductor device capable of improving properties during etching without damaging the original characteristics of a doped oxide film made of BSG, BPSG, PSG, or the like.
According to one aspect of the present invention, there is provided a method for manufacturing a semiconductor device comprising the steps of:
forming a doped oxide film as a hard mask material on a silicon substrate of a subject of etching;
coating a resist on said doped oxide film;
patterning said resist and using the patterned resist as an etching mask to etch said doped oxide film and obtain a patterned hard mask;
removing said resist;
baking the subject of etching to remove moisture contained in said doped oxide film; and
etching said substrate by using said patterned hard mask to make a recess.
According to another aspect of the present invention, there is provided a method for manufacturing a semiconductor device comprising the steps of:
forming a doped oxide film as a hard mask material on a silicon substrate of a subject of etching;
forming a protective cap layer on said doped oxide film;
coating a resist on said protective layer
patterning said resist and using the patterned resist as an etching mask to etch said protective cap layer and said doped oxide film and obtain a patterned hard mask;
removing said resist;
baking the subject of etching to remove moisture contained in said doped oxide film; and
etching said substrate by using said patterned hard mask to make a recess.
According to further aspect of the present invention, there is provided a method for manufacturing a semiconductor device comprising the steps of:
forming a doped oxide film as a first layer of an interlayer insulating film on a silicon substrate;
forming a silicon oxide film as a second layer of the interlayer insulating film on said doped oxide film;
forming a contact hole by patterning said doped oxide film and said silicon oxide film so that a surface of the silicon substrate is exposed;
performing baking to remove moisture contained in said doped oxide film; and
filling contact material in the contact hole.
The semiconductor device manufacturing method according to the invention is characterized in including the step of removing moisture from a doped oxide film as a hard mask material or an interlayer insulation film by baking it after forming it, and thereafter etching its substrate by using a patterned hard mask to make a recess.
REFERENCES:
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patent: 5425845 (1995-06-01), Wong
patent: 5554565 (1996-09-01), Liaw et al.
patent: 5926722 (1999-07-01), Jang et al.
patent: 6037236 (2000-03-01), Jang
patent: 6074931 (2000-06-01), Chang et al.
patent: 6074954 (2000-06-01), Lill et al.
patent: 6124206 (2000-09-01), Flietner et al.
patent: 7-307325 (1995-11-01), None
Matsumoto Takanori
Shimonishi Satoshi
Kabushiki Kaisha Toshiba
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
Smith Matthew
Yevsikov Victor V.
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