Method of manufacturing a semiconductor device

Details Method of manufacturing a semiconductor device Method of manufacturing a semiconductor device

1998-12-23

2001-06-26

Bowers, Charles (Department: 2813)

Semiconductor device manufacturing: process

Making passive device

Stacked capacitor

C438S253000, C257S309000, C257S311000, C257S532000

Reexamination Certificate

active

06251741

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally related a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device having a storage node.
2. Description of the Background Art
A capacitor including a storage node as a constituent element has been used for a memory IC, e.g., DRAM. The capacitor (hereinafter referred to as a “storage node capacitor”) comprises a storage node and a cell plate, both of which are formed from base material such as polysilicon, and a dielectric film which is interposed between the storage node and the cell plate and keeps them isolated from each other. With such a configuration, electric charges can be charged by the storage node and the cell plate by applying a voltage between them.
It is effective to ensure a larger surface area of the storage node capacitor in its occupation area for rendering the storage node capacitor compact. A greater surface area of the storage node can be ensured by forming the storage node into, e.g., the shape of a cylinder. Thus, a structure including a storage node formed into a cylindrical shape has been known as a structure of a storage node capacitor.
FIG. 10
shows the structure of a known cylindrical storage node
10
. The storage node
10
shown in
FIG. 10
can be provided by executing a series of operations described below.
(1) Formation of a sacrificial oxide layer (not shown) on a silicon oxide film
12
;
(2) Formation of a contact hole
14
which passes through the sacrificial oxide layer and the silicon oxide film
12
;
(3) Formation of a storage node contact
16
within the contact hole
14
;
(4) Formation of a space used for forming a storage node
10
by removing the sacrificial oxide layer in a cylindrical form;
(5) Formation of the storage node
10
into a cylindrical shape within the space; and
(6) Formation of the storage node
10
into a state shown in
FIG. 10
by etching away the sacrificial oxide layer surrounding the storage node.
It is effective to form the storage node
10
into an elongated shaped for providing a compact storage node capacitor having a large capacity and having the aforementioned conventional structure. However, the narrower the storage node
10
, the more the node becomes apt to tilt. Particularly, in the foregoing existing method, an etching effect is sometimes exerted on the silicon oxide film
12
as well as on the sacrificial oxide layer.
If an etching effect is exerted on the silicon oxide film
12
, the adhesion between the bottom surface of the storage node
10
and the silicon oxide film
12
is deteriorated, thus rendering the storage node more likely to tilt. For this reason, so long as the existing manufacturing method is used, it is difficult to make the storage node
10
compact while maintaining a high yield. More specifically, it is difficult to make a memory IC compact while maintaining a high yield.
SUMMARY OF THE INVENTION
The present invention has been conceived to solve the above-mentioned problem, and a general object of the present invention is to provide a novel and useful method of manufacturing a semiconductor device.
A more specific object of the present invention is to provide a method of manufacturing a semiconductor device which enables the manufacture of a compact memory IC at a high-yield by ensuring superior adhesion between a storage node and a dielectric film provided below the storage node.
The above object of the present invention is achieved by a method of manufacturing a semiconductor device. The method comprising the steps of forming a basic dielectric layer from a first dielectric material; forming on the basic dielectric layer an etch stopper film from a second dielectric material differing from the first dielectric film; forming on the etch stopper film a sacrificial dielectric layer from the first dielectric material; forming a space used for a formation of a storage node by removal of a predetermined area from the sacrificial dielectric layer until the etch stopper film becomes exposed; forming in the space a storage node from a capacitive material; and removing the sacrificial dielectric layer surrounding the storage node by means of an etching operation suitable for removal of the first dielectric material.
Other objects and further features of the present invention will be apparent from the following detailed description when read in conjunction with the accompanying drawings.


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patent: 5290729 (1994-03-01), Hayashide et al.
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patent: 5972769 (1999-10-01), Tsu et al.
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