Method of manufacturing a semiconductor device

Details Method of manufacturing a semiconductor device Method of manufacturing a semiconductor device

1987-03-13

1989-08-22

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 31, 437 33, 437 34, 437 59, 437 44, 357 34, 357 43, 148DIG11, H01L 2978, H01L 21225

Patent

active

048596302

ABSTRACT:
A method of manufacturing an integrated circuit is set forth comprising a field effect transistor having an insulated gate (35) and a further circuit element having a first (9) and a second electrode zone (14) of opposite conductivity types. Simultaneously with the gate (35) a conductive pattern (11) separated by an insulating layer (34) from the first electrode zone (9) is provided on the first electrode zone (9). This pattern (11) provides a pair of the edge of the doping opening (12) for the second electrode zone (14). A second insulating layer (16) is provided on the pattern (11) and is removed locally by anisotropic etching in such a manner that in the doping opening (12) edge portions (17) (16) are left. Subsequently, a conductive layer (22) for connection of the second electrode zone (14) is provided, which extends over the second insulating layer (16), over the pattern (11) and over the edge portions (17) (16 ) into the opening (12) of reduced size and on the second electrode zone (14). The contact opening for the second electrode zone (14) can thus be derved without alignment tolerance from the doping opening (12).

REFERENCES:
patent: 4346512 (1982-08-01), Liang et al.
patent: 4486942 (1984-12-01), Hirao
patent: 4497106 (1985-02-01), Momma et al.
patent: 4641420 (1987-02-01), Lee
Ghandhi, VLSI Fabrication Principles, John Wiley & Sons, N.Y., pp. 458-461.

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