Method of manufacturing a semiconductor device

Details Method of manufacturing a semiconductor device Method of manufacturing a semiconductor device

1979-06-20

1981-04-07

Rutledge, L. Dewayne

Metal treatment

Compositions

Heat treating

148187, 357 34, 357 91, H01L 21263, H01L 736

Patent

active

042604303

ABSTRACT:
An I.sup.2 L device is disclosed wherein the P type injector region of a PNP transistor is formed so as to be buried in an N.sup.- type epitaxial layer below the P type collector region of the PNP transistor, whereby the carrier injection efficiency of the transistor is improved and a high switching speed is obtained. The I.sup.2 L device further includes an inversed NPN transistor wherein the abovementioned P type collector region of the PNP transistor works as a base region of the NPN transistor, an N type collector region is formed in the P type base region, and the abovementioned P type injector region extends between the N.sup.- type epitaxial layer and an N.sup.+ type substrate except below the N type collector region so that the effective emitter portion of the NPN transistor is limited to a specific area immediately below the N type collector region, thereby to reduce the power consumption.

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