Method of manufacturing a semiconductor device

Details Method of manufacturing a semiconductor device Method of manufacturing a semiconductor device

1977-04-19

1979-04-24

Rutledge, L. Dewayne

Metal treatment

Compositions

Heat treating

357 34, 357 91, H01L 2972, H01L 21265

Patent

active

041510062

ABSTRACT:
A method of manufacturing a semiconductor device having a transistor structure in which the emitter zone comprises a lower-doped region adjoining the base zone and a more highly-doped region adjoining the surface. According to the invention, the more highly-doped part is obtained by the introduction of doping atoms through an undoped polycrystalline layer provided on the surface. Preferably, a thin silicon nitride or silicon oxide layer is provided between the surface and the polycrystalline silicon layer prior to providing the latter.

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Aggarwal, "Emitter. . . Impurity Conc. . . . ", IBM-TDB, 19 (1976) 162.
P. J. Krick, "MNOS . . . Structure, Wilh . . . Ion-Implantation", IBM Tech. Disc. Bull., 17, (1974) 1809.
J. L. Combasson et al., "Phys. Profile . . . Insulating Layers . . . Ion Analyser, "Ed. B. Crowder", Ion-Implantation In Semiconductors . . . ", Plenum Press, p. 285, 1972.

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