Method of manufacturing a semiconductor body comprising a mesa

Details Method of manufacturing a semiconductor body comprising a mesa Method of manufacturing a semiconductor body comprising a mesa

1990-08-29

1993-11-30

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437228, 437947, 437958, 437981, 156649, H01L 21308

Patent

active

052665186

ABSTRACT:
In the method according to the invention, the upper and thicker of two semiconductor layers is etched by means of a selective and preferential etchant, substantially no underetching occurring with respect to the mask. Subsequently, the lower and thinner semiconductor layer and a part of the upper semiconductor layer are converted by a substantially non-selective anodic oxidation into semiconductor material oxides, which are removed by means of an etchant which is non-selective with respect to the oxides formed, but is selective with respect to the semiconductor materials. As a result, mesas are obtained having a substantially flat side wall, the lateral dimension of these mesas being accurately determined by the size of the mask. Thus, particularly favourable results are obtained, especially in the InP/InGaAsP material system. The method according to the invention can be used very advantageously when the thinner layer forms part of a so-called multilayer quantum well structure.

REFERENCES:
patent: 4417385 (1983-11-01), Temple
patent: 4679305 (1987-07-01), Morizuka
patent: 4792958 (1988-12-01), Ohba et al.
IBM Technical Disclosure Bulletin "Gating Assenic Gate Field Effect Transistor Process Utilizing self-Aligned Epitaxial Contacts", vol. 31, No. 1, Dec. 1988, pp. 11-13.

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