Method of manufacturing a semiconductor Bi-CMOS device

Fishing – trapping – and vermin destroying

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437 31, 437 41, 437 57, 437162, 437240, 437982, 357 43, H01L 21331, H01L 21336

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049886339

ABSTRACT:
The collector region (20) of a bipolar transistor (T) and a first well region (3) for an insulated gate field effect transistor (IGFET) (P) are formed of one conductivity type at respective first and second device areas (10 and 12) of a semiconductor body (1a). After definition of an insulated gate (9), opposite conductivity type impurities are introduced to form source and drain regions (90 and 91) of the IGFET (P) and at the same time to dope a dopable layer (30) on the first device area (10) to form an opposite conductivity type doped layer (30) for forming an extrinsic base region (40). An insulating layer (50, 51) is then provided to cover the first and second device areas (10 and 12). Impurities for forming an intrinsic base region (41) and emitter region (80) of the bipolar transistor (T) are introduced through an opening (60, 61) in the insulating layer (50, 51) which also serves to mask the IGFET (P) from these impurities.

REFERENCES:
patent: 4752589 (1988-06-01), Schaber
patent: 4764482 (1988-08-01), Hsu
patent: 4902640 (1990-02-01), Sachitano et al.
Yamaguchi, T. et al., IEEE Transactions on Electron Devices, vol. 35, No. 8, Aug. 1988, pp. 1247-1256, Cole, B. C., Electronics, Feb. 4, 1988, pp. 55-67.

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