Semiconductor device manufacturing: process – Making device array and selectively interconnecting – Rendering selected devices operable or inoperable
Patent
1997-04-18
1999-08-10
Wilczewski, Mary
Semiconductor device manufacturing: process
Making device array and selectively interconnecting
Rendering selected devices operable or inoperable
438237, 438275, 438278, H01L 218246
Patent
active
059372800
ABSTRACT:
A ROM structure and its method of manufacture using separate parallel trench bit lines for increasing memory component density as well as using a diode as the fundamental memory unit, each diode having a junction formed inside a bit line with a forward biased voltage of about 0.4 V and a reverse biased voltage dependent upon the doping condition in an N.sup.- region. At a junction between a word line and a bit line, either an ON state or an OFF state diode memory unit is created depending on whether a contact opening in the insulating layer for connection between the two is formed or not. When a definite operating voltage is applied to the word line, the stored information bit in the diode memory unit can be read off from the bit line by sensing a cut-off or a conducting current representing previous program coding of the diode memory unit.
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United Microelectronics Corp.
Wilczewski Mary
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