Semiconductor device manufacturing: process – Making passive device – Resistor
Reexamination Certificate
1998-02-26
2001-06-12
Chaudhuri, Olik (Department: 2814)
Semiconductor device manufacturing: process
Making passive device
Resistor
C257S536000, C257S571000
Reexamination Certificate
active
06245628
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a method of manufacturing a resistor in a semiconductor device formed on a semi-insulating substrate, and more specifically relates to a method of forming a resistor having an adjustable resistance value.
BACKGROUND OF THE INVENTION
In a conventional forming method of a resistor between electrodes, a photo-resist having an opening for adjusting a resistance value is formed on a resistive area. Through the opening, the resistive area is etched so that a desirable resistance value is obtained by monitoring the resistance value.
The above conventional manufacturing method is described by referring to the cross sections in FIG.
3
(A
1
) through FIG.
3
(F
1
) and the plan views in FIG.
3
(A
2
) through FIG.
3
(F
2
).
First, as shown in FIG.
3
(A
1
) and FIG.
3
(A
2
), a photo-resist
3
having an opening
2
is formed on a semi-insulating substrate
1
such as GaAs, then an ion-plantation of an impurity is conducted into the semi-insulating substrate
1
in order to form a resistive contact area
4
of high impurity concentration.
Next, as shown in FIG.
3
(B
1
) and FIG.
3
(B
2
), the photo resist is removed, and a new photo resist
6
having an opening
5
is formed on the semi-insulating substrate
1
. Then, ions are planted into the semi-insulating substrate
1
in order to form a resistive area
7
of low impurity concentration.
As shown in FIG.
3
(C
1
) and FIG.
3
(C
2
), the photo-resist
6
is removed and a photo-resist
9
having an opening
8
for forming an electrode is formed on the semi-insulating substrate
1
.
As shown in FIG.
3
(D
1
) and FIG.
3
(D
2
), after metallic film being formed, the photo resist
9
is removed, and an ohmic electrode
10
is formed by Lift-Off method.
As shown in FIG.
3
(E
1
) and FIG.
3
(E
2
), a photo-resist
12
having an opening
11
across the entire resistive area
7
is formed. The opening
11
is used for adjusting a resistance value. Then the resistive area
7
is etched, and the resistance value is adjusted by monitoring a value thereof in order to get a desirable resistance value.
Finally, as shown in FIG.
3
(F
1
) and FIG.
3
(F
2
), the photo-resist
12
is removed in order to form a resistor between electrodes, of which resistance value has been adjusted to a desired value.
In the above method, when adjusting the resistance value by etching the resistive area
7
through the opening
11
which is across the entire resistive area
7
with monitoring the resistance value, the resistance value sharply increases after a certain period of etching, as shown in FIG.
4
. Accordingly, if an etching is slightly overtimed, the etching would penetrate the resistive area
7
, whereby the resistance value becomes infinite.
The etching time for adjusting the resistance value within a tolerance of a designed value, as shown in
FIG. 4
, is on the order of seconds. Therefore, it is difficult to control the resistance value, and the wide range of the resistance values resulting from the foregoing process contributes to lowering the yield rate.
As a result, there is a need to be able to control the resulting resistance value of the resistor formed between electrodes as described above so as to increase the yield rate when forming the resistance in an integrated circuit.
SUMMARY OF THE INVENTION
The present invention aims to improve controllability of a resistance value of a resistor formed between electrodes.
A method of forming a resistor according to the present invention comprises the following steps:
(a) Form a resistive area selectively on a semi-insulating substrate by ion-plantation or diffusion of an impurity,
(b) Form electrodes on both ends of the resistive area,
(c) Form a film having an opening on the resistive area so that the opening does not completely cross over the resistive area,
(d) Etch the resistive area exposed to the opening in order to adjust a resistance value of the resistive area.
A user can prevent a resistance value from reaching infinity, and have more deviation with regard to etching time (etching tolerance) through these steps, even if a user etches the resistive area as deep as penetrating thereof. As a result, the controlability of the resistance value as well as the yield rate of the resistor is increased.
REFERENCES:
patent: 3860465 (1975-01-01), Matzner et al.
patent: 4001762 (1977-01-01), Aoki et al.
patent: 4104085 (1978-08-01), Zandveld
patent: 4119440 (1978-10-01), Hile
patent: 4160984 (1979-07-01), Ladd, Jr. et al.
patent: 4191938 (1980-03-01), Gow, 3rd et al.
patent: 4418469 (1983-12-01), Fujita
patent: 4583107 (1986-04-01), Clarke
patent: 4637126 (1987-01-01), Lightstone
patent: 4679298 (1987-07-01), Zuleeg et al.
patent: 4742021 (1988-05-01), Burnham et al.
patent: 4921814 (1990-05-01), Ishikawa et al.
patent: 5081439 (1992-01-01), Natzle et al.
patent: 5089427 (1992-02-01), Schoenberg
patent: 5105242 (1992-04-01), Fujihara et al.
patent: 5330936 (1994-07-01), Ishitani
patent: 5468672 (1995-11-01), Rosvold
patent: 5496762 (1996-03-01), Sandhu et al.
patent: 5525831 (1996-06-01), Ohkawa et al.
patent: 5585302 (1996-12-01), Li
patent: 5602408 (1997-02-01), Watanabe et al.
patent: 5622884 (1997-04-01), Liu
patent: 5679593 (1997-10-01), Miller, Jr. et al.
patent: 5796131 (1998-08-01), Nakano et al.
patent: 5808332 (1998-09-01), Kohno et al.
patent: 5830792 (1998-11-01), Tseng
patent: 5834356 (1998-11-01), Bothra et al.
patent: 5837570 (1998-11-01), Asano
patent: 5886373 (1999-03-01), Hosogi
patent: 5895250 (1999-04-01), Wu
patent: 5900641 (1999-05-01), Hara et al.
patent: 5942772 (1999-08-01), Nishii et al.
patent: 5946572 (1999-08-01), Terasawa
patent: 5976944 (1999-11-01), Czagas et al.
patent: 113820 (1974-09-01), None
patent: 401155601A (1989-06-01), None
Fukui Takeshi
Furukawa Hidetoshi
Ueda Daisuke
Chaudhuri Olik
Duy Mai Anh
Matsushita Electronics Corporation
McDermott & Will & Emery
LandOfFree
Method of manufacturing a resistor in a semiconductor device does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of manufacturing a resistor in a semiconductor device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of manufacturing a resistor in a semiconductor device will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2485626