Method of manufacturing a read only semiconductor memory device

Details Method of manufacturing a read only semiconductor memory device Method of manufacturing a read only semiconductor memory device

1991-05-01

1992-03-10

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 27, 437 45, 437 48, 357 2312, H01L 2170

Patent

active

050949713

DESCRIPTION:

BRIEF SUMMARY
FIELD OF THE INVENTION

This invention relates to a method of manufacturing a read only semiconductor memory device, and more particularly to a method of manufacturing a semiconductor memory device such as a NAND type mask ROM of the two layer layer electrode structure suitable for miniaturization.


BACKGROUND OF THE INVENTION

In order to allow the read only memory (ROM) to be of a large scale structure, it is most suitable to adopt a cell structure of the NAND type in which the cell size is reduced by connecting in series transistors functioning as a memory cell. The principle of the operation of such a cell is schematically shown in FIGS. 1 and 2.
FIG. 1 shows the cell system of the NAND type mask ROM, and FIG. 2 shows a readout of this ROM. In these figures, reference numerals 11 denote bit lines, 22 word lines, 33 depletion type transistors, and 44 enhancement type transistors, respectively. In the case of reading data in the cell A in these figures, gates W.sub.1, W.sub.3 and W.sub.4 are caused to have a high voltage (e.g., 5 V), and the gate W.sub.2 is caused to have zero volts. In addition, the drain (bit line b.sub.1) is stepped up. At this time, if a current flows, the cell A is considered to be comprised of a depletion type transistor, and, on the other hand, if no current flows, the cell A is considered to be comprised of an enhancement type transistor. In this mask ROM, discrimination between "0" and "1" of data is made in dependency upon whether the transistor is of the depletion type or the enhancement type. In order to allow the transistor to be of depletion type, impurities of a conductivity type opposite to that of the substrate are ion-implanted into the portion below the electrode of the substrate. This ion implantation will be called ROM implantation hereinafter.
To miniaturize such a NAND type cell, it is sufficient to allow the pitches between transistors connected in series to be as small as possible. To reduce such pitches, two-layer polysilicon was conventionally employed as the gate electrode.
The process of the conventional example for preparing a device of such a structure is shown in FIGS. 3A to 3C.
As seen from FIG. 3A, e.g., a p-type silicon substrate or a p-type well within an n-type substrate may be used as the substrate 1. A gate oxide film 2 is formed on the substrate 1. Thereafter, a resist 3 is coated or covered over the region except for a region where a transistor desired to be of depletion type is to be formed. By using the resist 3 as a mask, impurity 4 of a conductivity type opposite to that of the substrate, e.g. phosphorus is ion-implanted into the region where an impurity layers 4A are to be formed, e.g., under the condition of an acceleration voltage of 40 KeV, and a dose quantity of 3.times.10.sup.13 cm.sup.-2 (ROM implantation).
As seen from FIG. 3B, a polysilicon layer 5A is then formed so that its thickness is equal to about 4000 .ANG.. This layer 5A is processed by the reactive ion etching (RIE) to form first gate electrodes 5.
Thereafter, as seen from FIG. 3C, an inter-gate-electrode insulating film 6 is formed by thermal oxidation at a temperature of 900.degree. C. Then, a polysilicon layer 7A having a thickness of 4000 .ANG. is formed. This layer 7A is processed by RIE to form second gate electrodes 7. At the time of forming the second gate electrodes 7, RIE processing is carried out so that the end portions of the second gate electrodes 7 overlap with the upper parts of the first gate electrodes 5.
Let now consider how the lower limit of the space S1 between first electrodes 5 is determined by the conventional process described above.
In FIG. 4, S1 represents a space between first electrodes 5, S2 a ROM implantation mask space, L.sub.min a line minimum value of the ROM implantation mask, Leff.sub.min a transistor minimum effective channel length, .DELTA.x an expansion of impurities implanted by the ROM implantation, and .DELTA.M an alignment margin. In FIG. 4, the respective values are assumed as follows.
The processing limit of lithography is assume

REFERENCES:
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patent: 4506436 (1985-03-01), Balceman, Jr. et al.
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patent: 4818716 (1989-04-01), Okuyama et al.
patent: 4898840 (1990-02-01), Okuyama et al.
patent: 4904615 (1990-02-01), Okuyama et al.
patent: 5002896 (1991-03-01), Naruke

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