Method of manufacturing a passive integrated matching...

Details Method of manufacturing a passive integrated matching... Method of manufacturing a passive integrated matching...

2007-10-02

2007-10-02

Nguyen, Cuong (Department: 2811)

Semiconductor device manufacturing: process

Forming bipolar transistor by formation or alteration of...

Including passive device

C438S171000, C438S190000, C438S210000, C438S393000

Reexamination Certificate

active

11179685

ABSTRACT:
An impedance matching network is integrated on a first die and coupled to a second die, with the first and second dies mounted on a conductive back plate. The impedance matching network comprises a first inductor bridging between the first and second dies, a second inductor coupled to the first inductor and disposed on the first die, and a metal-insulator-metal (MIM) capacitor disposed on the first die. The MIM capacitor has a first metal layer coupled to the second inductor, and a second metal layer grounded to the conductive back plate. A method for manufacturing the integrated impedance matching network comprises the steps of forming an inductor on a die, forming a capacitor on the die, coupling the capacitor to the inductor, coupling the die bottom surface and the capacitor to a conductive plate, and coupling the inductor to another inductor that bridges between the die and another die.

REFERENCES:
patent: 6512285 (2003-01-01), Hashemi et al.
patent: 2005/0236689 (2005-10-01), Sugiura et al.

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