Method of manufacturing a packaging structure for electronic...

Details Method of manufacturing a packaging structure for electronic... Method of manufacturing a packaging structure for electronic...

2006-08-01

2006-08-01

Coleman, W. David (Department: 2823)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

Making plural separate devices

C257SE21503

Reexamination Certificate

active

07084009

ABSTRACT:
A wiring substrate including a predetermined wiring pattern, an electronic parts connection terminal on an element forming surface of which is flip-chip connected to the wiring pattern, an insulating film for covering the electronic parts, a via hole formed in a predetermined portion of the electronic parts and the insulating film on the connection terminal, and an overlying wiring pattern formed on the insulating film and connected to the connection terminal via the via hole.

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patent: 2001/0004130 (2001-06-01), Higashi et al.
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patent: 2002/0127839 (2002-09-01), Umetsu et al.
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patent: 1 248 295 (2002-10-01), None
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patent: 2001-177045 (2001-06-01), None
patent: 2001-196525 (2001-07-01), None

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