Method of manufacturing a multi-chip semiconductor package

Details Method of manufacturing a multi-chip semiconductor package Method of manufacturing a multi-chip semiconductor package

2002-06-12

2004-02-10

Elms, Richard (Department: 2824)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

Including adhesive bonding step

C438S127000

Reexamination Certificate

active

06689637

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor package and, more particularly to a milti-semiconductor package comprising a plurality of semiconductor chips and a fabrication method thereof.
2. Description of the Prior Arts
Recently, electronic apparatuses using semiconductor chips (semiconductor device), for example computer, PCS, cellular phone and PDA, have become of high performance, simpler to fabricate and smaller and more compact in the size. Accordingly, semiconductor chips and semiconductor packages applied to the electronic system also become smaller and more compact.
As is generally known, package methods of semiconductor chips include Multi Chip Module (MCM) package and Multi Chip Package (MCP).
As shown in
FIG. 3
, the MCM package is fabricated by a method in which a plurality of semiconductor chips
302
,
304
and
306
are adhered on a base
300
such as a thin metal film, ceramic or substrate using wire bonding, tape bonding and flip chip bonding.
In
FIG. 3
, the first semiconductor chip
302
is adhered by wire bonding, the second semiconductor chip
304
is adhered by tape bonding and the third semiconductor chip
306
is adhered by flip chip bonding, wherein a reference numeral
308
represents a PGA input/output terminal and
310
represents a BGA input/output terminal.
The MCP is fabricated by a method in which two or more semiconductor chips are mounted in a package of defined size, wherein a plurality of semiconductor chips are mounted on a lead frame or substrate using wire bonding. Referring to
FIG. 4
, a plurality of semiconductor chips
404
a
and
404
b
are loaded on a substrate
402
using wire bonding and pads of the semiconductor chips
404
a
and
404
b
are connected to an external lead
406
by using wire
408
, wherein the resulting structure is surrounded by epoxy molding compound (EMC)
400
.
However, the conventional MCM package and the MCP have limitations in realizing a small and compact size due to the structure that a plurality of semiconductor chips are adhered on a base such as a thin metal film, ceramic or substrate using wire bonding, tape bonding or a flip chip bonding, or that a plurality of semiconductor chips are mounted on a substrate using wire bonding and then, surrounded by epoxy molding compound.
And, the conventional package has a structure that a pad of semiconductor chip and the external lead are connected by wire, thereby there arises a problem of lowering the quality and reliability of semiconductor package (that is, degradation of electrical properties) and especially, the conventional package using EMC has a problem that reliability of semiconductor package is lowered drastically by alpha particles generated in the epoxy molding compound (EMC) and pollution in active region of device by EMC.
SUMMARY OF THE INVENTION
Therefore, the present invention has been proposed to solve the above problems and the primary objective of the present invention is to provide a semiconductor package capable of realizing a small and compact size and improving the reliability and the fabrication method of the same.
The semiconductor package of the present invention comprises: a main semiconductor chip operating as a lead frame or a substrate and having a plurality of main chip pads on the outer peripheral part thereof; one or more sub semiconductor chips adhered to a predetermined part of the main semiconductor chip and having a plurality of sub chip pads on the outer peripheral part thereof; an insulating layer formed on the main semiconductor chip in a shape surrounding the sub semiconductor chip to expose the main chip pads and the sub chip pads; a plurality of metal patterns electrically connecting the exposed main chip pad to the sub chip pad or one sub chip pad to another sub chip pad, each metal pattern comprising a lower barrier layer formed on the main chip pad, a seed layer formed on the lower barrier layer, and a metal layer formed on the seed layer; and a plurality of solder lands formed on a predetermined part of the plurality of metal patterns.
The method of fabricating the semiconductor package according to the present invention comprises the steps of: applying an adhesive on a predetermined part of main semiconductor chip operating as a lead frame or a substrate and having a plurality of main chip pads on the outer peripheral part thereof; adhering one or more sub semiconductor chips having a plurality of sub chip pads on the outer peripheral thereof on the adhesive; forming an insulating layer to surround the one or more sub semiconductor chips and to expose the main chip pads and the sub chip pads; forming a plurality of metal patterns electrically connecting the main chip pad to the sub chip pad and one sub chip pad to another sub chip pad; applying a sealant on the entire surface of the main semiconductor chip having the plurality of metal patterns and then exposing the upper part of the metal pattern; forming a solder land on the exposed upper part of metal pattern; and adhering a solder ball on the upper part of the solder land.


REFERENCES:
patent: 5786230 (1998-07-01), Anderson et al.
patent: 6121682 (2000-09-01), Kim
patent: 6365432 (2002-04-01), Fukutomi et al.

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