Metal treatment – Process of modifying or maintaining internal physical... – Chemical-heat removing or burning of metal
Patent
1978-02-02
1979-01-02
Rutledge, L. Dewayne
Metal treatment
Process of modifying or maintaining internal physical...
Chemical-heat removing or burning of metal
29576E, 29576W, 29578, 148187, 148190, 148191, 357 44, 357 46, 357 48, 357 89, 357 90, 357 92, H01L 2120, H01L 21225, H01L 2174
Patent
active
041325737
ABSTRACT:
A monolithic integrated circuit is formed having semiconductor components disposed in surface regions of a semiconductor body, said regions being electrically isolated from the remaining semiconductor body by a pn-junction plane. The regions into which the semiconductor components are formed are electrically isolated by heavily doping surface areas of a substrate with phosphorus, antimony and/or arsenic impurities which are of the opposite conductivity from the substrate. After said doping, an epitaxial layer having a conductivity opposite to that of the substrate is formed over the entire substrate surface with a doping concentration lower than that of the substrate so that during subsequent high temperature processing steps, the substrate impurity out-diffuses into the epitaxial layer and the phosphorus of the heavily doped surface areas diffuses downwardly into the substrate to form a step-like pn-junction surface alternately extending into the substrate and into the epitaxial layer. During subsequent processing operations, an impurity of the same conductivity type as used in the substrate is diffused downwardly from the surface of the epitaxial layer to meet the out-diffused substrate impurity to complete the isolation of surface regions of the semiconductor body into which the semiconductor components are formed.
REFERENCES:
patent: 3423650 (1969-01-01), Cohen
patent: 3481801 (1969-12-01), Hugle
patent: 3723199 (1973-03-01), Vora
patent: 3767486 (1973-10-01), Imaizumi
patent: 3909807 (1975-09-01), Fulton
patent: 3922565 (1975-11-01), Berger et al.
patent: 3928091 (1975-12-01), Tachi et al.
patent: 4032372 (1977-06-01), Vora
Hilbiber, D., "High-Performance ----Integrated Circuits" IEEE Trans. on Electron Devices, v. Ed-14, No. 7, Jul. 1967, pp. 381-385.
Czorny, B., "Epitaxy-Versatile Technology for Integrated Circuits", R.C.A. Engineer, vol. 13, No. 3, Oct.-Nov. 1971, pp. 28-32.
Berger et al., "Base Ring Transistor and Method of Production", I.B.M. Tech. Discl. Bull., vol. 14, No. 1, Jun. 1971, p. 302.
Frantz et al., "Monolithic Electric Circuit", IBID., vol. 14, No. 6, Nov. 1971, p. 1684.
Murata Manufacturing Co. Ltd.
Rutledge L. Dewayne
Saba W. G.
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