Fishing – trapping – and vermin destroying
Patent
1993-07-19
1996-05-07
Thomas, Tom
Fishing, trapping, and vermin destroying
437231, 437228, 437238, H01L 2144
Patent
active
055146244
ABSTRACT:
A method of manufacturing an interlayer dielectric for microelectronic devices having multiple conducting layers provides a planarized surface for deposition of subsequent layers and further prevents cracking of spin-on-glass by limiting spin-on-glass thickness to about 0.4 .mu.m or less. A first dielectric layer is formed over a first conducting layer by means of reacting Si(OC.sub.2 H.sub.5).sub.4 and O.sub.2 at approximately 9 torr between 370.degree. C. to 400.degree. C., and a second dielectric layer is formed over the first dielectric layer by a method different than that used to form the first dielectric layer. After etching back the second dielectric layer, a spin-on-glass layer is formed. Spin-on-glass layer is etched back to provide a planar surface and a third dielectric layer is formed over the spin-on-glass layer. The resulting surface is ready for contact hole formation, deposition and patterning of subsequent conductive and insulating layers.
REFERENCES:
patent: 4283249 (1981-08-01), Ephrath
patent: 4872947 (1989-10-01), Wang et al.
patent: 5070036 (1991-12-01), Stevens et al.
patent: 5219792 (1993-06-01), Kim et al.
patent: 5266525 (1993-11-01), Morozumi
patent: 5270254 (1993-12-01), Chen et al.
Wolf et al., vol. I, Silicon Processing for the VLSI Era Lattice Press, 1986.
Kawai et al, "Interlayered Dielectric Planarization with TEDS-CVD and SOG" 1988 IEEE VLSI Multilevel Interconnection Conference, Jun. 1988, pp. 419-425.
S. Wolf, Silicon Processing for the VLSI Era, vol. 2, Lattice Press, Sunset Beach, CA, 1990, pp. 198-199, 232-234, 279-283, 532-533.
J. J. Hsieh, et al., "Directional Deposition of Dielectric Silicon Oxide by Plasma Enhanced TEOS Process", 1989 IEEE-VMIC Conference, Jun. 1989, pp. 411-415.
B. L. Chin et al., "Plasma TEOS Process for Interlayer Dielectric Applications", Solid State Technology, Apr. 1988, pp. 119-122.
Gurley Lynn A.
Seiko Epson Corporation
Thomas Tom
LandOfFree
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