Method of manufacturing a metal-insulator-semiconductor utilizin

Metal treatment – Process of modifying or maintaining internal physical... – Chemical-heat removing or burning of metal

Patent

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

29571, 148188, 357 23, 357 58, 357 59, 427 86, 427 85, 4272554, 4272557, H01L 2120, H01L 21225

Patent

active

042499682

ABSTRACT:
A method of making a metal-oxide-semiconductor device is disclosed. A thin silicon dioxide insulating layer is formed on the surface of a planar silicon wafer. A first layer of intrinsic polycrystalline silicon is deposited over the dioxide layer, and a second layer of doped polycrystalline silicon is deposited over the intrinsic layer, thereby forming the gate. Subsequent hot processing steps result in diffusion of a portion of the dopant from the doped polycrystalline layer into and throughout the intrinsic layer so as to dope the latter. A metal contact layer is then deposited onto the gate and in superimposed vertical alignment with respect to the thin silicon dioxide insulating layer. The instrinsic nature of the first polycrystalline layer reduces grain growth and void formation in the polycrystalline silicon and thereby prevents the silicon dioxide from being attacked by hydrofluoric acid seeping through voids in the polycrystalline layer during subsequent processing. The yield for the manufacture of devices having thin oxide gates is substantially improved.

REFERENCES:
patent: 3519901 (1970-07-01), Bean et al.
patent: 3738880 (1973-06-01), Laker
patent: 3783050 (1974-01-01), Nanba et al.
patent: 3980507 (1976-09-01), Carley
patent: 4074300 (1978-02-01), Sakai et al.
patent: 4087571 (1978-05-01), Kamins et al.
patent: 4143178 (1979-03-01), Harada et al.
patent: 4180826 (1979-12-01), Shappir
Chou et al., "Variable Threshold Field-effect Transistor" I.B.M. Tech. Discl. Bull., vol. 13, No. 6, Nov. 1970, p. 1485.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Method of manufacturing a metal-insulator-semiconductor utilizin does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of manufacturing a metal-insulator-semiconductor utilizin, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of manufacturing a metal-insulator-semiconductor utilizin will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-1664099

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.