Method of manufacturing a metal-insulator-semiconductor device u

Metal working – Method of mechanical manufacture – Assembling or joining

Patent

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

29578, 29591, 148 15, 148174, 148188, 357 23, 357 58, 357 59, 427 85, 427 86, 427 93, 4272554, H01L 2120, H01L 21225

Patent

active

043543090

ABSTRACT:
A method of making a metal-oxide-semiconductor device is disclosed. A thin silicon dioxide insulating layer is formed on the surface of a planar silicon wafer. A first layer of intrinsic polycrystalline silicon is deposited over the dioxide layer, and a second layer of doped polycrystalline silicon is deposited over the intrinsic layer, thereby forming the gate. Subsequent hot processing steps result in diffusion of a portion of the dopant from the doped polycrystalline layer into and throughout the intrinsic layer so as to dope the latter. A metal contact layer is then deposited onto the gate and in superimposed vertical alignment with respect to the thin silicon dioxide insulating layer. The intrinsic nature of the first polycrystalline layer reduces grain growth and void formation in the polycrystalline silicon and thereby prevents the silicon dioxide from being attacked by hydrofluoric acid seeping through voids in the polycrystalline layer during subsequent processing. The yield for the manufacture of devices having thin oxide gates is substantially improved.

REFERENCES:
patent: 3523838 (1970-08-01), Heidenreich
patent: 3638301 (1972-02-01), Matsuura
patent: 3675319 (1972-07-01), Smith
patent: 3738880 (1973-06-01), Laker
patent: 3980507 (1976-09-01), Carley
patent: 4057895 (1977-11-01), Ghezzo
patent: 4143178 (1979-03-01), Harada et al.
Chou et al., "Variable Threshold Field-Effect Transistor", IBM Tech. Discl. Bull., vol. 13, No. 6, Nov. 1970, p. 1485.
Solid-State Electronics, vol. 21, No. 9, Sep. 1978, pp. 1173-1174, "A Technique for Producing Polysilicon Patterns with Bevelled Edge Profiles Using Wet Etching" by B. A. Boxall.
Chemical Abstracts, vol. 83, No. 24, Dec. 1975, p. 521, "Preparation and Properties of Phosphorus-Doped Polycrystalline Silicon Films" by M. Kuisl et al.
Journal of Electrochemical Society, vol. 126, No. 8, Aug. 1979, pp. 1415-1418, "Polysilicon Interconnection Technology for IC Device" by H. Yamanaka et al.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Method of manufacturing a metal-insulator-semiconductor device u does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of manufacturing a metal-insulator-semiconductor device u, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of manufacturing a metal-insulator-semiconductor device u will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-1333587

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.