Method of manufacturing a memory FET with shorted source and dra

Details Method of manufacturing a memory FET with shorted source and dra Method of manufacturing a memory FET with shorted source and dra

1982-06-18

1986-09-02

Ozaki, George T.

Metal working

Method of mechanical manufacture

Assembling or joining

29576B, 29577C, 148 15, 148187, H01L 2138, H01L 21425

Patent

active

046087486

ABSTRACT:
A method of manufacturing a semiconductor device having a plurality of MOS transistors which construct a memory section. After forming a plurality of MOS transistors on a semiconductor substrate, source regions and drain regions of given MOS transistors are shorted in accordance with a requested program. An insulating film is subsequently formed on the MOS transistors and an interconnection wiring layer is further formed thereon.

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patent: 4230504 (1980-10-01), Kuo
patent: 4246044 (1981-01-01), Yanase
patent: 4268950 (1981-05-01), Chatterjee et al.
patent: 4365405 (1982-12-01), Dickman et al.
patent: 4397887 (1983-08-01), Aytac et al.

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