Method of manufacturing a memory cell for a dynamic type random

Details Method of manufacturing a memory cell for a dynamic type random Method of manufacturing a memory cell for a dynamic type random

1986-08-28

1988-03-15

Ozaki, George T.

Fishing, trapping, and vermin destroying

427 52, 437 52, H01L 21425

Patent

active

047313420

ABSTRACT:
A method of manufacturing a MOS semiconductor device which comprises a first step of forming a p-type well region in the surface of an n-type silicon substrate, a second step of forming a field oxide layer surrounding part of the surface of the well region, a third step of ion-implanting a n-type impurity into the surface of the well region, to reduce the carrier density of the well region in the vicinity of the ion-implanted without changing the conductivity type of the well region, a fourth step of forming a gate electrode insulatively on the ion-implanted surface of the well region, and a fifth step of forming the n.sup.+ -type source and drain regions in the ion-implanted surface of the well region. The third step of this manufacturing method uses the field oxide layer for implanting the n-type impurity, as a mask.

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Meguro et al., "Hi-CMOS III Technology", Technical Digest of International Electron Devices Meeting (IEDM), 1984, pp. 59-62, Dec. 1984.

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