Method of manufacturing a logic circuit including at least one f

Details Method of manufacturing a logic circuit including at least one f Method of manufacturing a logic circuit including at least one f

1981-08-21

1983-09-06

Andrews, M. J.

Metal working

Method of mechanical manufacture

Assembling or joining

29574, 29577C, 29580, 29583, 29589, 357 3, 357 15, 357 55, H01L 21302

Patent

active

044021275

ABSTRACT:
A method of manufacturing a logic circuit having at least one field effect transistor connected in series with at least one saturable resistor, wherein an active semiconductor layer is formed with a predetermined thickness on a semi-insulating substrate, ohmic contacts are deposited to produce source and drain regions for the resistor and the transistor, a Schottky contact is deposited between the resistor source and drain ohmic contacts to form a gate region which is then electrically connected to the resistor source contact by means of a metal connection, whereupon the localized thickness of the active layer is measured by measuring the drain-source current to the resistor upon application of a predetermined voltage thereto and a groove then cut between the source and drain contacts of the field effect transistor to obtain a predetermined channel depth from the bottom of the groove to the semi-insulating substrate. Then, a Schottky contact is deposited in the groove of the field effect transistor and the logic circuit completed conventionally.

REFERENCES:
patent: 3767984 (1973-10-01), Shinoda et al.
patent: 3813585 (1974-05-01), Tarui et al.
patent: 3959807 (1976-05-01), Upadhyayula et al.
patent: 4028556 (1977-06-01), Cachier et al.
patent: 4069493 (1978-01-01), Bobenrieth
patent: 4300064 (1981-11-01), Eden
patent: 4321613 (1982-03-01), Hughes et al.

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