Method of manufacturing a lightly doped drain MOS transistor

Details Method of manufacturing a lightly doped drain MOS transistor Method of manufacturing a lightly doped drain MOS transistor

1995-07-26

1997-07-22

Niebling, John

Fishing, trapping, and vermin destroying

437151, 437164, H01L 21265, H01L 21225, H01L 21385, H01R 2122

Patent

active

056503474

ABSTRACT:
A method of manufacturing a lightly doped drain MOS transistor having the double shallow junction is disclosed including the steps of forming a gate and a gate insulating film on a semiconductor substrate of a first conductivity type, sequentially; forming, on the top and sidewalls of the gate, on side edges of the gate insulating layer, and on the substrate, an insulating film including two kinds of impurities whose diffusivity and conductivity type are different from each other forming a cap insulating film on the insulating film; performing the heat treatment process thereby to form impurity regions of a second conductivity type and impurity regions of the first conductivity type surrounding the impurity regions of the second conductivity type, on both sides of the gate in the substrate; etching the insulating film and the cap insulating film thereby to form sidewall spacers on both sides of the gate; and ion-implanting an impurity of the second conductivity type in the substrate thereby to form impurity regions of the second conductivity type adjacent to the impurity regions.

REFERENCES:
patent: 4588455 (1986-05-01), Genser
patent: 4597824 (1986-07-01), Shinada et al.
patent: 4994404 (1991-02-01), Sheng et al.
patent: 5086005 (1992-02-01), Hirakawa
patent: 5183777 (1993-02-01), Doki et al.
patent: 5297956 (1994-03-01), Yamabe et al.
"Potential Profile Engineering for Quarter Micron Buried Channel pMOSFETs with n Regions in the Channel" K. Okabe, T. Ikezawa, I. Sakai and M. Fukuma.

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