Method of manufacturing a layer sequence and a method of...

Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching

Reexamination Certificate

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C719S323000, C719S323000, C216S062000, C216S079000

Reexamination Certificate

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07144820

ABSTRACT:
A method of manufacturing a layer sequence having a first and a second laterally confined structure comprises the steps of providing a first layer on a first surface portion of a substrate, which first layer is doped with dopant of a first type of conductivity, providing a second layer on a second surface portion of the substrate, which second layer is free of dopant of the first type of conductivity, forming a third layer on the first layer, which third layer is free of dopant of the first type of conductivity, and forming a fourth layer on the second layer, which forth layer is doped with dopant of the first type of conductivity. The first layer and the third layer are etched, thereby patterning the first and third layer to form the first laterally confined structure. The second layer and the forth layer are etched, thereby patterning the second and fourth layer to form the second laterally confined structure.

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patent: 6168998 (2001-01-01), Park
patent: 6261885 (2001-07-01), Cheek et al.
patent: 6703269 (2004-03-01), Brown et al.
patent: 6790577 (2004-09-01), Nakamura
patent: 00/02782 (2000-04-01), None
Wolf, Silicon Processing for the VLSI Era, 2002, Lattice Press, vol. 4, pp. 244-245.
Callister, Materials Science and Engineering, 1997, John Wiley & Sons, 4th ed., pp. 605-609.

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