Method of manufacturing a heterojunction bipolar transistor invo

Details Method of manufacturing a heterojunction bipolar transistor invo Method of manufacturing a heterojunction bipolar transistor invo

1987-09-16

1988-12-06

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 90, 437133, 437228, 437 81, 148DIG11, 148DIG26, 148DIG50, 357 34, 156652, H01L 21302

Patent

active

047896434

ABSTRACT:
A heterojunction bipolar transistor and method of manufacturing the same is disclosed in which, a semi-insulation layer and an external base layer sequentially epitaxially grown on a collector layer are selectively mesa-etched through a mask of an insulation film provided with an opening so that the external base layer, the semi-insulation layer and the collector layer are selectively exposed. Subsequently an internal base layer and an emitter layer are selectively epitaxially grown in sequence on the exposed regions of the external base layer, the semi-insulation layer and the collector layer. An emitter electrode is formed in a self-aligned manner through the opening of the insulation film. Thus, transistor performance is improved and element size accuracy is improved.

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patent: 4593457 (1986-06-01), Birittella
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patent: 4663381 (1987-05-01), Birittella
patent: 4716445 (1987-12-01), Sone
patent: 4746626 (1988-05-01), Eda et al.
S. S. Tan and A. G. Milnes: IEEE Transactions on Electron Devices, vol. ED-30 (1983), P1289-P1294.
P. M. Asbeck, D. L. Miller, R. J. Anderson and F. H. Eisen: IEEE Electron Device Letters, vol. EDL-5 (1984), P310-P312.

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