Method of manufacturing a heterojunction bipolar transistor

Details Method of manufacturing a heterojunction bipolar transistor Method of manufacturing a heterojunction bipolar transistor

1999-08-23

2001-04-24

Powell, William (Department: 1765)

Semiconductor device manufacturing: process

Chemical etching

Vapor phase etching

C438S713000, C438S718000, C438S720000, C438S724000

Reexamination Certificate

active

06221783

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of manufacturing a heterojunction bipolar transistor, and more particularly to a method of manufacturing a heterojunction bipolar transistor capable of effectively reducing a junction capacitance between the base and the emitter which greatly affects a maximum oscillation frequency, even in future applications where the size of devices is reduced to accomodate a very high speed characteristic.
2. Description of the Prior Art
As multimedia communication services such as internet, on-line game, home banking, etc. have developed rapidly, a need for transmitting various informations in high speed have been increased and thus communication system capable of handling this need have been rapidly developed. Therefore, it is essential to make core electronic elements to be mounted into the system with a very high speed and a very high frequency. A heterojunction bipolar transistor (referred below to HBT) is used for various digital and analog communication circuits as a very high speed and very high frequency element. In recent, it is known that a cut-off frequency f
T
and a maximum oscillation frequency f
max
are more than 100 GHz, respectively, for AlGaAs/GaAs or InGaP/GaAs HBT, and more than 200 GHz, respectively, for InP/InGaAs or InAlAs/InGaAs HBT. Upon comparing HBT with other semiconductor devices such as field effect transistor (FET), etc, the HBT is not limited by lithography technology and also has an unique high speed characteristic since it is based on the longitudinal control of electrons on a heterojunction epitaxial. However, in order to maximize these advantages, it is necessary that the time taken when electrons pass through the base and the collector depletion layers must be shorten, and the emitter, the base and the collector ohmic resistances must be reduced, and also effective processes for reducing the emitter-base capacitance, the base-collector capacitance, and various parasitic elements, etc. must be developed. As a method into which the above requirements are simply quantized, it may be expressed into the following equation, f
max
=(f
T
/8&pgr;R
B
C
BC
)
½
. Where R
B
represents the base resistance and C
BC
represents the base-collector junction capacitance. As can be seen from the above equation, if the base-collector junction capacitance C
BC
is reduced, f
max
which greatly affects a high speed characteristic of circuits can be substantially improved. As practical process technologies for reducing the external base-collector junction capacitance, undercutting of the external base region, ion injection isolation against the external base region and the external base regrowth, etc. have been used.
Now, the conventional methods for manufacturing these HBTs will be explained by reference to
FIGS. 1 through 4
.
FIGS. 1 through 4
are cross-sectional views for showing the method of manufacturing the conventional HBT.
FIG. 1
is a cross-sectional view showing a first embodiment of a conventional heterojunction bipolar transistor, which shows a structure of a device commonly used.
First, a buffer layer
10
is grown on a semiconductor substrate
1
. Then, a subcollector layer
20
, a collector layer
30
, a base layer
40
, an emitter layer
50
and an emitter cap layer
60
are sequentially grown on the buffer layer
10
to form a HBT structure. An emitter electrode
65
is then formed at a selected region on the HBT epitaxial substrate. Then a selected region of the emitter cap layer
60
and the emitter layer
50
is subjected to mesa-etching process to form a base electrode
55
at a selected region on the base layer
40
. Then, the selected region of the base layer
40
and the collector layer
30
is subjected to mesa-etching process thereby to form a collector electrode
35
at a selected region on the subcollector layer
20
. Finally, the resulting structure is subjected to isolation mesa-etching process. At this time, the collector electrode
35
is made of a different material from that of the emitter electrode
65
and the base electrode
55
.
However, the above method never uses any technology for improving external parasitic resistance or capacitance.
FIG. 2
is a cross-sectional view showing a second embodiment of a conventional heterojunction bipolar transistor.
First, a buffer layer
110
is formed on a semiconductor substrate
100
. Then, a subcollector layer
120
, an epitaxial layer
120
(which acts as a barrier layer upon overetching) for selective etching, a collector layer
130
, a base layer
140
, an emitter layer
150
and an emitter cap layer
160
are sequentially grown on the buffer layer
110
to form a HBT structure. After an emitter electrode
165
is formed at a selected region on the HBT epitaxial substrate, a selected region on the emitter cap layer
160
and the emitter layer
150
is subjected to mesa-etching process thereby to form a base electrode
155
at a selected region on the base layer
140
. After the selected region of the base layer
140
and the collector layer
130
is subjected to mesa-etching process, both sides of the collector layer
130
are etched through overetching process thereby to form a collapsed region
132
. A collector electrode
135
is then formed on an epitaxial layer
125
. Finally, the resulting structure is subjected to isolation mesa-etching process.
The above mentioned overetching process has been developed by Michigan University in U.S.A., etc. First, the process defines the emitter layer
150
and the base layer
140
. Then, it uses a high rate of selective etching characteristic to the collector layer
130
of the base layer to over-etch into the inner side of the collector layer
130
, so that it can reduce the effective base-collector junction capacitance. This method greatly affects the device characteristics depending on the repeatability and uniformity of the process.
FIG. 3
is a cross-sectional view showing a third embodiment of a conventional heterojunction bipolar transistor.
First, a buffer layer
210
is formed on a semiconductor substrate
200
. Then, a subcollector layer
220
, a collector layer
230
, a base layer
240
, an emitter layer
250
and an emitter cap layer
260
are sequentially grown on the buffer layer
210
to form a HBT epitaxial structure. After an emitter electrode
265
is formed at a selected region on the HBT epitaxial substrate, the selected region on the emitter cap layer
260
and the emitter layer
250
is subjected to mesa-etching process. Then, an insulating area
232
is formed at a selected region on the base layer
240
and the collector layer
230
through impurity injection process using the emitter electrode
265
as a mask. After a base electrode
255
is then formed at a selected region on the insulating area
232
, the selected region is subjected to mesa-etching process. Then, a collector electrode
235
is selectively formed on the subcollector layer
220
. The resulting structure is subjected to isolation mesa-etching process.
The above mentioned ion implantation isolating technology is one that accelerates proton ion H
+
, helium ion He
+
, boron ion B
+
, etc. with a high level of energy into an external base layer into which p-type impurity of high concentration is doped and an external collector layer into which n-type impurity is doped, using the emitter electrode
265
as a mask, so that the region
232
within which electrical channels are disrupted can be defined. Since this method has its purpose to significantly reduce the effective junction capacitance between the base layer
240
and the collector layer
230
, it can make a significant advance in view of research and development. However, it requires activation thermal process for restoring the damage of the surface of the base layer
240
in order to deposit the base electrode
235
. Therefore, since this method may destruct a abrupt junction of the entire epitaxial structure, there is a great danger in adopting as a practical application.
FIG. 4

Affiliated with

Also associated with

Rating

Method of manufacturing a heterojunction bipolar transistor does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of manufacturing a heterojunction bipolar transistor, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of manufacturing a heterojunction bipolar transistor will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2485655