Semiconductor device manufacturing: process – Forming bipolar transistor by formation or alteration of... – On insulating substrate or layer
Reexamination Certificate
2002-09-18
2003-09-16
Nhu, David (Department: 2818)
Semiconductor device manufacturing: process
Forming bipolar transistor by formation or alteration of...
On insulating substrate or layer
C438S257000, C438S381000
Reexamination Certificate
active
06620698
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a method for manufacturing a flash memory, more particularly, to the method for manufacturing the contact in a flash memory with buried line to simplify the steps of the process and to increase the density of the semiconductor devices.
2. Description of the Related Art
Modern semiconductor devices are designed and fabricated toward a trend of size minimization so that more and more devices can be packed in a chip with a limited area. In order to shrink the device sizes of these semiconductor devices and pack these semiconductor devices into one chip as more as possible, various conventional processes of fabricating these semiconductor devices have been improved or even replaced with new processes to overcome many nature limits. Semiconductor devices such as logic devices and memory devices particularly have the necessaries of size decrease and integration increase so that they can operate more powerfully and store more data.
As the density of these semiconductor devices continually increases, the multilevel interconnect structures of these semiconductor devices also has more and more levels. Meanwhile, the problems of the process window decrease and the reducing of planarization are also raised.
FIG. 1
shows a cross-sectional diagram of conventional flash memory whose capacitors are not shown. A substrate
100
, the first gate
102
a
, the second gate
102
b
, a source region
101
a
, a drain region
101
b
, a shallow trench isolation (STI) layer
120
, interlevel dielectric (ILD) layers
104
, a contact
106
, an active region
107
, a buried conductive line
108
, and a metal line
112
. The active region
107
is connected to the drain
101
b
by using the buried conductive line
108
and is used to be a connected point between the traditional contact
106
and the buried conductive line
108
. The first gate
102
a
is formed on the substrate
100
and there is a tunnel dielectric layer
105
between the substrate
100
and the first gate
102
a
. The second gate
102
b
is formed on the first gate
102
a
and there is an oxide
itride/oxide layer
103
between the first gate
102
a
and the second gate
102
b
. The contact
106
is formed in the interlevel dielectric layer
104
and is used to connect to the metal line
112
and the active region
107
.
In the traditional flash memory structure, because the active region must be used to be the connected point between the traditional contact and the buried conductive line, a volume of the traditional flash memory is not reduced successfully and the traditional flash memory is formed by using more process steps. This condition will decrease the proceeding efficiency of the traditional flash memory.
In view of the drawbacks mentioned with the prior art process, there is a continued need to develop new and improved processes that overcome the disadvantages associated with prior art processes. The requirements of this invention are that it solves the problems mentioned above.
SUMMARY OF THE INVENTION
It is therefore a main objective of the invention to provide a simplified process of forming contacts and lead lines of semiconductor devices.
The second objective of this invention is to increase the integration and the die density of semiconductor devices and decrease the overhead of the semiconductor devices.
The third objective of this invention is to improve planarization of semiconductor devices and increase process window of the semiconductor devices.
The fourth objective of the invention is to reduce a volume of the semiconductor element.
The further objective of the invention is to increase the proceeding efficiency of the semiconductor element process.
To achieve these objects, and in accordance with the purpose of the invention, the invention uses a method comprising: providing a substrate which comprises the first dielectric layer; forming a trench into the substrate to form a isolation region therein; forming a photoresist layer over the substrate; transferring a line pattern connecting adjacent active regions of the substrate into the photoresist layer to expose the substrate; implanting ions into the substrate at a tilt angle to form a buried conductive line therein; forming the second dielectric layer on the buried conductive line and filling of the trench; forming the first gate on the first dielectric layer and forming a oxide
itride/oxide layer on the first gate, wherein the first gate is the floating gate of the flash memory; forming a source region and a drain region in the substrate which is on both sides of the first dielectric layer; removing the partial second dielectric layer to form a contact therein, wherein the top of the contact is wider than the bottom of the contact and the bottom of the contact and the buried conductive line are connected with each other; using an ions bombarding to clean the sidewalls and the bottom of the contact; and manufacturing a polysilicon layer in the contact and forming the second gate on the oxide
itride/oxide layer to finish processes of the flash memory, wherein the second gate the control gate of the flash memory.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.
REFERENCES:
patent: 5366915 (1994-11-01), Kodama
patent: 5783457 (1998-07-01), Hsu
patent: 5936889 (1999-08-01), Choi
Chang Kent Kuohua
Chen Chao-Yang
Macronix International Co. Ltd.
Nhu David
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