Active solid-state devices (e.g. – transistors – solid-state diode – Organic semiconductor material
Reexamination Certificate
1998-08-17
2002-08-06
Crane, Sara (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Organic semiconductor material
C257S410000, C257S613000, C438S099000
Reexamination Certificate
active
06429450
ABSTRACT:
BACKGROUND OF THE INVENTION
The invention relates to a method of manufacturing a field-effect transistor substantially consisting of organic materials.
The invention also relates to a field-effect transistor substantially consisting of organic materials.
The invention further relates to an integrated circuit (IC) comprising such a field-effect transistor (FET).
An integrated circuit comprising field-effect transistors substantially consisting of organic materials, in short organic field-effect transistors, is well suited for those electronic applications where using an integrated circuit manufactured using silicon technology would be prohibitively expensive. Examples include electronic bar codes.
As is well known by those skilled in the art, if an IC is to perform its task, it is imperative that the integrated logic gates, such as invertors, NOR and NAND gates, attain voltage amplification at the operating voltage. In order to attain voltage amplification, each individual field-effect transistor must be operated in a saturated regime, which is the regime where the channel transconductance exceeds the channel conductance.
A method of the type mentioned in the opening paragraph, which provides an organic FET satisfying said condition for voltage amplification is known from an article by Garnier et al. published in Science, vol. 265 (1994), pp. 1684-1686. In said known method a 1.5 &mgr;m thick polyester film is framed and is printed on both sides with a graphite-filled polymer ink, so as to form a 10 &mgr;m thick gate electrode on the one side and a source and drain electrode on the other side. Between the source and drain a 40 nm semiconducting sexithiophene layer is then deposited using flash evaporation.
A disadvantage of the known method is that the organic FETs provided by the method satisfy the condition for voltage amplification only at rather high (negative) source drain voltages. Typically, the difference is 30 V or higher. For many electronic applications, such as battery operated applications, such a voltage is too high. Also, the method is not very practical, not least because it involves framing and printing on a layer of only 1.5 &mgr;m. Such a thin film is very fragile and easily ruptures while being handled, leading to a defective device.
SUMMARY OF THE INVENTION
An object of the invention is, inter alia, to provide a novel method of manufacturing a field-effect transistor substantially consisting of organic materials. The novel method should enable, in a practical manner, the manufacture of an organic FET satisfying the condition of voltage amplification at a source drain voltage difference significantly less than 30 V, in particular less than 10 V.
The object of the invention is achieved by a method of manufacturing a field-effect transistor substantially consisting of organic materials on a substrate surface, said method comprising the steps of:
providing an electrically insulating substrate surface,
applying an organic first electrode layer accommodating a source and drain electrode and demonstrating a patchwork pattern of electrically insulating and conducting areas,
applying an organic semiconducting layer preferably of a thickness so selected that the condition for voltage amplification is satisfied at source drain voltages less than 10 V, and especially,
applying an organic electrically insulating layer having a thickness less than 0.3 &mgr;m,
applying an organic second electrode layer accommodating a gate electrode.
Using the method in accordance with the invention, it is possible to manufacture FETs satisfying the condition of voltage amplification at source drain voltages below 10 V, for example, about 2.5 V.
The invention is based on the insight that a very thin electrically insulating layer, that is a layer having a thickness of 0.3 &mgr;m or less, is required if an organic FET is to satisfy the condition of voltage amplification at a source drain voltage difference of less than 10 V. It is further based on the insight that such a thin insulating layer can only be obtained in a practical manner if (in contrast to the known method in which the insulating layer is used as a substrate for depositing the electrodes) the thin insulating layer is supported by a substrate throughout the manufacture of the FET. Most conveniently, the insulating layer is applied to a surface which is substantially planar. Manufacturing the first electrode layer in the form of a patchwork pattern of electrically insulating and conducting areas provides a substantially planar surface (the difference in thickness between the insulating and conducting areas being 0.05 &mgr;m or less).
The method in accordance with the invention is simple and cost effective. It involves few steps. The first and second electrode layer, as well as the insulating and semiconducting layer, can be, and preferably are, all applied from solution using coating techniques known per se, such as spin-coating, dip-coating, spray-coating, curtain-coating, silkscreen-printing, offset-printing, Langmuir Blodgett and the doctor blade technique.
The field-effect transistor obtained by employing the method in accordance with the invention operates in the usual manner. The semiconducting layer comprises an area, the channel, which interconnects the source and the drain electrode. The gate electrode is electrically insulated from the channel by means of the insulating layer and overlaps the channel. If a voltage is applied between the source and drain electrode, a current, i.e. the source drain current, will flow through the channel. By applying a gate voltage, an electric field is established across the semiconducting layer which will, depending on the polarity of both the gate voltage and the charge carriers, modify the free charge carrier distribution in the channel, thereby changing the resistivity of the channel and the source drain current. If the source drain voltage is increased while the gate voltage is kept constant, the source drain current will begin to saturate and at some point the condition of voltage amplification, i.e. the channel transconductance exceeding the channel conductance, is satisfied.
The first electrode layer comprises electrically insulating and conducting areas, which may be of any convenient shape. The source and drain electrode are accommodated by separate conducting areas. In order to increase the channel width, thus allowing more current between source and drain, the source and drain electrode are preferably interdigitated.
In order to minimize the leakage current and the voltage drop between separate conducting areas, in particular between the source and drain electrodes, the sheet resistance of the insulating areas needs to be as high as possible. A suitable sheet resistance exceeds 10
10
&OHgr;/square, or better 10
12
&OHgr;/square or better still 10
13
&OHgr;/square.
The specific conductivity of the conducting areas of the electrode layer is chosen such that the source drain current is substantially determined by the resistivity of the channel. A suitable specific conductivity of the conducting areas is 0.1 S/cm or better 1 S/cm or better still more than 10 S/cm.
Applying the patchwork patterned first electrode layer is for example done by applying a semiconducting polymer in an insulating state from solution, applying and patterning a photoresist layer photolithographically and introducing conducting areas by selective indiffusion of a dopant which converts locally the polymer from its insulating to a conducting state.
Preferably, the patchwork patterned first electrode layer is applied without using the elaborate technique of photolithography. This is achieved by an embodiment of the method in accordance with the invention which is characterized in that the organic first electrode is applied by performing the method steps of
applying an organic radiation-sensitive layer,
irradiating said radiation-sensitive layer according to a desired pattern, thereby forming an organic first electrode layer accommodating a source and drain electrode and demonstrating a patchwork pattern
De Leeuw Dagobert M.
Drury Christopher J.
Mutsaers Cornelius M. J.
Bartlett Ernestine C.
Crane Sara
Koninklijke Philips Electronics , N.V.
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