Method of manufacturing a device comprising MIS transistors havi

Details Method of manufacturing a device comprising MIS transistors havi Method of manufacturing a device comprising MIS transistors havi

1990-09-25

1991-05-14

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437 41, 437233, 437191, 357 233, 156643, H01L 21265

Patent

active

050155997

ABSTRACT:
Method is set forth of manufacturing a device comprising MIS transistors having a projecting gate on the weakly doped parts of source and drain regions.
A method comprising the deposition of a first and a second polycrystalline conducting layer, which are separated by an insulating layer.
According to the invention, gate islands (20) are formed in the second polycrystalline layer (14) and the ion implantation of the weakly doped portions (21, 22) of the source and drain zones is effected through the assembly of the insulating layer (13) and the first polycrystalline layer (12). A third polycrystalline layer (23) is then deposited, which layer contacts both the island of the second polycrystalline layer (14) and the first polycrystalline layer (12). Widened gate islands (26) are finally marked off by means of the insulating spacer technique (25), in which islands there remain only present the portions (23') of the third polycrystalline layer (23) in the shape of an "L". The highly doped portions (28, 29) of the source and drain zones are then implanted.

REFERENCES:
patent: 4818715 (1989-04-01), Chao
patent: 4837180 (1989-06-01), Chao
patent: 4906589 (1990-03-01), Chao
patent: 4907048 (1990-03-01), Huang
patent: 4925807 (1990-05-01), Yoshikawa
patent: 4963504 (1990-10-01), Huang
patent: 4971922 (1990-11-01), Watabe et al.
Huang et al., "A Novel Submicron LDD Transistor with Inverse T-Gate Structure", IEDM, 1986, pp. 742-745.
Izawa et al., "The Impact of Gate-Drain Overlapped LDD (GOLD) for Deep Submicron VLSI's", IEDM 1987, pp. 38-41.

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