Semiconductor device manufacturing: process – Making passive device – Trench capacitor
Reexamination Certificate
2000-09-13
2001-03-20
Le, Vu A. (Department: 2824)
Semiconductor device manufacturing: process
Making passive device
Trench capacitor
C438S396000, C438S398000, C438S665000
Reexamination Certificate
active
06204141
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device. More particularly, the present invention relates to a method of manufacturing a deep trench capacitor.
2. Description of the Related Art
In a Dynamic random Access Memory (DRAM), the capacitor is the signal storage center. The more electric charges are stored in the capacitor, the less likely it is to be influenced by noise (for example, the soft errors created by particle &agr;) when retrieving data, and the refresh frequency of the DRAM can also be reduced.
However, when the semiconductor process enters a deep sub-micron manufacturing, the dimensions of the devices are shrunk correspondingly. In light of the former DRAM storage memory structure, it also reflects that the space for accommodating a capacitor is becoming smaller. Therefore, how to maintain the capacitor so that there is ample capacitance becomes an important topic for manufacturing a semiconductor device that is about 0.25 &mgr;m and smaller. In order to increase the area of the capacitor, a popular method is provided to increase the capacitance of the capacitor.
The stacked capacitor and the trench-type capacitor are conventionally used to increase the surface area of the capacitor. The stacked capacitor has many different three-dimensional structures such as a crown, fin, cylinder, or a spread, while the trench-type capacitor has different three-dimensional structures such as a deep trench or a buried strap trench. Even if the various structures of the above described capacitors fulfill the requirements of designs for relatively high DRAM density, however, under the limited design rules of the device dimensions, it is very difficult to solely use these structures to manufacture a capacitor of 256 MB or as much as 1 GB DRAM.
SUMMARY OF THE INVENTION
The invention provides a method of manufacturing a deep trench capacitor with a large capacitance, which has a unique combination of a deep trench with a fin structure, so that it is applicable towards the manufacturing of a 256 MB (or greater) DRAM.
A second object of the present invention is to provide a method of manufacturing a deep trench capacitor. By using a rugged polysilicon layer, the inner trench surface forms fin openings and forms a conformal lower electrode on the trench surface, thereby increasing the surface area of the lower electrode of the capacitor.
Yet another object of the present invention is to provide a method of manufacturing a deep trench capacitor. A thermal oxidation rate of a rugged polysilicon layer of a trench surface within a silicon substrate is greater than the thermal oxidation rate of silicon substrate. Thus, a relatively thick oxide layer is formed on the surface of the rugged polysilicon layer, and the oxide layer formed on the silicon substrate in the trench is removed. Etching is performed on the exposed trench surface, thereby forming fin openings on the inner trench surface. A conformal lower electrode is formed on the trench surface, hence, increasing the surface area of the lower electrode of the capacitor.
As embodied and broadly described herein, the invention provides a method of manufacturing a deep trench capacitor. This method includes forming a first silicon oxide layer, and subsequently forming a first trench in the substrate. A discrete rugged polysilicon layer is formed on the first trench surface. A second silicon oxide layer is formed on the surface of the rugged polysilicon layer. The exposed substrate surface is etched to form second trenches in the substrate. Thereafter, the first silicon oxide layer and second silicon oxide layer are removed. A first conductive layer is formed conformal to the surfaces of the first trench and second trenches. A dielectric layer and a second conductive layer are sequentially formed on the first conductive layer, thereby completing the capacitor manufacturing process.
In accordance with the method proposed in the above-described invention, the thermal oxidation rate of the rugged polysilicon layer that is greater than the thermal oxidation rate of the silicon substrate. Therefore, a thick silicon oxide layer is formed on the rugged polysilcon surface. The silicon oxide layer formed on the silicon substrate in the trench is removed. The exposed trench surface is subsequently etched, thereby causing the trench surface to be uneven. A lower electrode is formed conformal to the trench surface. Hence, the surface area of the lower electrode is increased. This is the first time that using discrete rugged polysilicon layer and different thermal oxidation rates to manufacture a capacitor structure with the combined deep trench and fin three-dimentional characteristics.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 5691228 (1997-11-01), Ping et al.
patent: 5877061 (1999-03-01), Halle et al.
patent: 6033967 (2000-03-01), Li et al.
patent: 6087240 (2000-07-01), Gilchrist
patent: 6103570 (2000-08-01), Sandhu et al.
patent: 6103571 (2000-08-01), Li et al.
patent: 6146968 (2000-11-01), Lu et al.
Huang Jiawei
J C Patents
Le Vu A.
Lebentritt Michael S.
Taiwan Semiconductor Mfg. Co. Ltd.
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