Method of manufacturing a damage free buried contact using salic

Details Method of manufacturing a damage free buried contact using salic Method of manufacturing a damage free buried contact using salic

1995-08-11

1997-10-21

Niebling, John

Fishing, trapping, and vermin destroying

437192, 437193, H01L 2128

Patent

active

056796072

ABSTRACT:
A manufacturing process for a CMOS cell with a buried contact uses highly selective etching techniques in combination with a thin oxide etching stop to prevent damage to the buried contact during the etching process. A cavity is formed in the oxide layer between the buried contact and its adjacent interconnect polysilicon element. A self-aligning silicide process (salicide) is used to coat the interconnect polysilicon, the cavity, and the buried contact, to form a continuous electrical connection between the interconnect polysilicon and the buried contact.

REFERENCES:
patent: 5053349 (1991-10-01), Matsuoka
patent: 5064776 (1991-11-01), Roberts
patent: 5126285 (1992-06-01), Kosa et al.
patent: 5162259 (1992-11-01), Kolar et al.
patent: 5348896 (1994-09-01), Jang et al.
patent: 5536683 (1996-07-01), Lin et al.
"Limitation of Spacer Thickness in Titanium Salicide ULSI CMOS Technology", Janmye James Sung and Chih-Yuan Lu, IEEE Electron Device Letters, vol. 10, No. 11, Nov. 1989, pp. 481-483.

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