Semiconductor device manufacturing: process – Making passive device – Stacked capacitor
Reexamination Certificate
1999-01-04
2001-06-26
Fourson, George (Department: 2823)
Semiconductor device manufacturing: process
Making passive device
Stacked capacitor
Reexamination Certificate
active
06251742
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to semiconductor capacitors, and more specifically, to a method of making a high capacitance memory cell capacitor with a cup-shape.
BACKGROUND OF THE INVENTION
In dynamic random access memory (DRAM) fabrication technology, continuous efforts are being undertaken to manufacture a capacitor having larger capacitance in a smaller area. Generally, a DRAM cell includes a capacitor and a transistor, the capacitor utilized for storing electric charge, and the transistor used for accessing the charge stored in the capacitor. Either the source or drain of the transistor is connected to one terminal of the capacitor. The other terminal of the transistor and the transistor gate electrode are connected to external connection lines called a bit line and a word line, respectively.
The capacitor type that is most typically used in DRAM memory cells are planar capacitors, which are relatively simple to manufacture. With the advent of ultra large scale integrated (ULSI) DRAM devices, the sizes of memory cells has gotten smaller and smaller such that the area available for a single memory cell has become very small.
For very small memory cells, planar capacitors become very difficult to use reliably. Similarly, the size of the charge capable of being stored by the capacitor decreases. This results in the capacitor being very susceptible to alpha particle radiation. Additionally, as the capacitance decreases, the charge held by the storage capacitor must be refreshed often. Therefore, a variety of methods of forming capacitors have been proposed to overcome the aforesaid problems. For a stacked memory cell, Ogawa has proposed a memory cell with a crown shape having fins formed therein, entitled “METHOD OF FABRICATING A SEMICONDUCTOR DEVICE HAVING A CAPACITOR IN A STACKED MEMORY CELL”, U.S. Pat. No. 5,164,337. The method can provides a capacitor with larger surface area; however, it is relatively complicated to form a capacitor with fin structures.
A further prior art approaches to overcome these problems has resulted in the development of a capacitor-over-bit-line (COB) cell with a hemispherical-grain (HSG) polysilicon storage node (see “A CAPACITOR-OVER-BIT-LINE CELL WITH HEMISPHERICAL-GRAIN STORAGE NODE FOR 64 Mb DRAMs”, M. Sakao etc. Microelectronics Research Laboratories, NEC Corporation). The HSG-Si is deposited by low pressure chemical vapor deposition at the transition temperature from amorphous-Si to polycrystalline-Si. Conventional methods of increasing area by using HSG is insufficient. If the HSG-Si storage node is compared with a planar node, the increase of the surface area of the node is up to about two at best.
SUMMARY OF THE INVENTION
A method for manufacturing an integrated circuit capacitor is disclosed. The method comprises the steps of: forming an etching stop layer over a semiconductor substrate; forming a dielectric layer on said etching stop layer, wherein said dielectric layer has a higher etching selectivity to said etching stop layer; patterning a photoresist on said dielectric layer; anisotropically etching said dielectric layer by using said photoresist as an etching mask, thereby generating a slot in said dielectric layer; isotropically etching said dielectric layer by using said photoresist as an etching mask, thereby expanding said slot to form a cup-shape cavity in said dielectric layer; stripping said photoresist; forming a first conductive layer along a surface of said etched dielectric layer; filling material into said cup-shape cavity, wherein an upper portion of said first conductive layer is left exposed by said material; removing the exposed upper portion of said first conductive layer using said material as a mask; removing said etched dielectric layer and said material to generate a conductive cup-shape structure; forming a dielectric film on said conductive cup-shape structure; and forming a second conductive layer over said dielectric film.
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Christensen O'Connor Johnson & Kindness PLLC
Fourson George
Garcia Joannie A.
Vanguard International Semiconductor Corporation
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