Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Isolation by pn junction only
Reexamination Certificate
2000-11-27
2003-02-18
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Isolation by pn junction only
C438S418000, C438S269000, C438S523000, C438S524000, C438S597000, C438S607000, C438S637000, C438S641000, C438S672000, C438S674000, C438S675000, C438S684000
Reexamination Certificate
active
06521508
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates generally to a method of manufacturing a semiconductor device. More particularly, the present invention relates to a method of manufacturing a contact plug in a semiconductor device using selective epitaxial growth of silicon (hereinafter called “SEG”) process in a high-integration semiconductor device.
2. Description of the Prior Art
It is said that a SEC technology is highly evaluated in view of reduction in a cell size and simplification in a manufacturing process.
A contact plug of a conventional SAC (self-aligned contact) method is formed in such a manner that doped silicon is deposited in a contact hole and is polished, and polysilicon is separated by chemical mechanical polishing (CMP) process.
However, formation of the contact plug by this SAC method has a manufacturing problem in implementing a contact hole having a high aspect ratio in a device technology of below 0.16 &mgr;m. More particularly, the conventional process of manufacturing a contact plug usually includes performing CMP process for flattening the surface of an interlayer insulating film, forming a contact plug, depositing doped polysilicon and then performing CMP process again. That is, there is a problem that the conventional process must perform twice CMP process that is expensive in the unit price in process. Also, when CMP process and etching of the contact hole are performed, the hard mask and the spacer functioning as an etch barrier on the gate electrode usually employs an oxide material of the interlayer insulating film and a nitride material having an etch selectivity. At this time, though the thickness of the nitride film must be increased to sufficiently act as an etch barrier, it is difficult to control the etching uniformity of the contact by reactive ion etching (hereinafter called “RIE”) since the aspect ratio is increased when the contact hole is manufactured.
Recently, a method of manufacturing a contact plug using SEC has been developed as one method of reducing CMP process while solving the drawback in the conventional contact plug.
Thus, by forming the contact plug using SEG, the height of the hard mask nitride film acting as a barrier can be reduced. Also, as the polishing process for an interlayer insulating film can be performed at the height of the gate electrodes the aspect ratio of the contact plug for the plug can be lowered, thus improving stability in forming the contact plug in SAC process. Additionally, as the silicon polishing process can be omitted, simplification of process can be obtained.
Though, in case of using LPCVD method using SEG, there are some problems that must be solved.
One of them is to secure selectivity depending on a pattern material (i.e., material forming a window so that SEG can be grown). Generally, SEG can be significantly varied depending on selectivity, defects due to thermal stress, shape of facet formation, etc. In other words, in case that the nitride film is used as the pattern material in the SEG process, it is difficult to secure selectivity for silicon below 800° C.
Also, as the thermal coefficient of expansion (TCE) of the nitride film is much higher than that of silicon, there is a problem that creation of SEG defects depending on variation in the temperature could not be prohibited.
Additionally, when doping such as P is performed in-situ during SEG process, there is a problem that the speed of SEG is reduced since securing of selectivity is difficult. Also, if the sidewall of the contact hole is formed of a nitride material, there is a problem that a corner filling is weakened since facet (54°) of (111) phase is grown.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a method of manufacturing a semiconductor device using SEG process capable of reducing generation of defects during a manufacturing process of SEG, by depositing an oxide film of a plasma type having a good step coverage on a nitride film, implementing RIE and cleaning process and then performing SEG process so that selectivity and a process margin for the nitride film acting as an etch barrier can be secured when a contact plug is formed using SEG process.
In order to accomplish the above object, a method of manufacturing a contact plug in a semiconductor device using SEG process according to the present invention is characterized in that it comprises the steps of forming a nitride film at a predetermined in a semiconductor substrate region except for the region in which a contact plug will be formed; forming an USG film on the entire surface of the substrate in which the nitride film is formed by chemical enhanced vapor deposition method of a plasma method; etching the USG film by reactive ion etch method to expose the surface of silicon in the structure; and forming a contact plug by performing in-situ process while performing selective epitaxial growth method for the silicon film exposed through the contact hole in the structure.
According to the present invention, if a pattern layer being an underlying structure in a contact hole having a high aspect ratio in a high integration semiconductor device is a nitride film, a shallow USG film is formed on its surface by plasma method to thus significantly increase selectivity of the nitride film during SEG process. Thereby, it can reduce defects caused by thermal stress and formation of facets in the nitride during SEC process to increase a plug process margin.
REFERENCES:
patent: 4728623 (1988-03-01), Lu et al.
patent: 4738937 (1988-04-01), Parsons
patent: 4918029 (1990-04-01), Kim
patent: 5004702 (1991-04-01), Samata et al.
patent: 5030583 (1991-07-01), Beetz
patent: 5032538 (1991-07-01), Bozler et al.
patent: 5045494 (1991-09-01), Choi et al.
patent: 5047367 (1991-09-01), Wei et al.
patent: 5272109 (1993-12-01), Motoda
patent: 5322802 (1994-06-01), Baliga et al.
patent: 5322814 (1994-06-01), Rouse et al.
patent: 5340754 (1994-08-01), Witek et al.
patent: 5378652 (1995-01-01), Samata et al.
patent: 5393681 (1995-02-01), Witek et al.
patent: 5432121 (1995-07-01), Chan et al.
patent: 5435856 (1995-07-01), Rouse et al.
patent: 5494837 (1996-02-01), Subramanian et al.
patent: 5508225 (1996-04-01), Kadoiwa
patent: 5527723 (1996-06-01), Witek et al.
patent: 5567652 (1996-10-01), Nishio
patent: 5599724 (1997-02-01), Yoshida
patent: 5627102 (1997-05-01), Shinriki et al.
patent: 5627395 (1997-05-01), Witek et al.
patent: 5633201 (1997-05-01), Choi
patent: 5744377 (1998-04-01), Sekiguchi et al.
patent: 5753555 (1998-05-01), Hada
patent: 5773350 (1998-06-01), Herbert et al.
patent: 5804470 (1998-09-01), Wollesen
patent: 6180453 (2001-01-01), Sung et al.
patent: 6235575 (2001-05-01), Kasai et al.
patent: 6248643 (2001-06-01), Hsieh et al.
patent: 6306723 (2001-10-01), Chen et al.
patent: 2002/0031916 (2002-03-01), Ohkubo et al.
patent: 54-158880 (1979-12-01), None
patent: 2-37745 (1990-02-01), None
patent: 2-260667 (1990-10-01), None
patent: 8-236728 (1996-09-01), None
patent: 10-107219 (1998-04-01), None
patent: 11-97519 (1999-04-01), None
Cheong Woo Seock
Roh Eui Beom
Finnegan Henderson Farabow Garrett & Dunner L.L.P.
Gurley Lynne A.
Hyundai Electronics Industries Co,. Ltd.
Niebling John F.
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