Method of manufacturing a complementary MIS transistor

Details Method of manufacturing a complementary MIS transistor Method of manufacturing a complementary MIS transistor

1993-02-24

1994-08-30

Thomas, Tom

Fishing, trapping, and vermin destroying

437 44, 437 34, 437 56, 148DIG82, H01L 2170

Patent

active

053428021

ABSTRACT:
A high withstanding voltage MIS transistor, including an offset region and a double offset region in a region of a semiconductor substrate. The region of the semiconductor substrate has a first conductivity type. The offset region connects to a drain region, and has a second conductivity type. An impurity concentration of the offset region is lower than that of the drain region. The double offset region has the first conductivity type. At least a portion of the double offset region overlaps with the offset region. An impurity concentration of the double offset region is higher than that of the region of the semiconductor substrate. The disclosed structure has an improved current gain of the MIS transistor is improved.
A method of manufacturing a CMOS having such a MIS transistor decreases the number of the manufacturing steps because the double offset region of a first conductivity type channel MIS transistor and the offset region of a second conductivity type channel MIS transistor are simultaneously formed.

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