Method of manufacturing a CMOS device with zero soft error rate

Details Method of manufacturing a CMOS device with zero soft error rate Method of manufacturing a CMOS device with zero soft error rate

2010-10-20

2011-12-27

Bryant, Kiesha (Department: 2891)

Semiconductor device manufacturing: process

Forming schottky junction

Combined with formation of ohmic contact to semiconductor...

C438S169000, C438S570000, C438S580000, C438S581000, C438S582000, C438S583000

Reexamination Certificate

active

08084342

ABSTRACT:
A CMOS device and method of manufacture is provided for producing an integrated circuit that is not susceptible to various soft errors such as single-event upsets, multi-bit upsets or single-event latchup. The CMOS device and method utilizes a new and novel well architecture in conjunction with metal source/drain electrodes to eliminate soft errors. In one embodiment, the CMOS device uses a first metal source/drain material for the NMOS device and a second metal source/drain material for the PMOS device. The CMOS device further uses a multi-layered well-structure with a shallow N-well and a buried P-well for the PMOS device and a shallow P-well and a buried N-well for the NMOS device.

REFERENCES:
patent: 7521765 (2009-04-01), Tsutsumi et al.
patent: 2004/0041226 (2004-03-01), Snyder et al.
patent: 2004/0171240 (2004-09-01), Snyder et al.
patent: 2005/0079668 (2005-04-01), Jung

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