Electrolysis: processes – compositions used therein – and methods – Electrolytic coating – Coating selected area
Reexamination Certificate
2001-12-27
2003-12-23
Nguyen, Nam (Department: 2827)
Electrolysis: processes, compositions used therein, and methods
Electrolytic coating
Coating selected area
C205S118000, C205S131000
Reexamination Certificate
active
06666964
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a circuit board such as a high-density printed circuit board, multi-layer printed circuit board and flexible printed circuit board, which is built into electronic equipment such as a semi-conductor package such as IC cards, portable information terminal, a coil circuit board built into a thin-type motor and various magnetic sensors, and a circuit board such as those used for CSP, BGA or the like, and a method of manufacturing the same. Particularly, the present invention relates to a circuit board using an insulating substrate provided with via holes and a wiring conductor comprising a gold-plated layer, and a method of manufacturing same.
BACKGROUND OF THE INVENTION
FIG. 4
is a plan view of a conventional circuit board. Also,
FIG. 5A
is a partly enlarged plan view of the circuit board, and
FIG. 5B
is a partly enlarged cross-sectional view of the circuit board.
FIG. 5B
is a cross-sectional view of
FIG. 5A
cut by a
5
B—
5
B line.
In
FIGS. 5A and 5B
, the conventional circuit board
20
comprises an insulating substrate
1
, wiring conductor
2
, via-hole
3
, and solder resist
4
.
As shown in
FIG. 4
, the circuit board
20
has an insulating substrate
1
such as a polyimide film tape on which a specific pattern of wiring conductor
2
is repeatedly formed.
Also, as shown in
FIGS. 5A and 5B
, the insulating substrate
1
has via-holes
3
. Further, a semiconductor chip (not shown), wiring conductor
2
and solder resist
4
to maintain the insulation are laminated on the central portion of the specific pattern of the wiring conductor
2
. For the purpose of bonding with the semiconductor chip, a bonding area
5
is formed at the end of the wiring conductor
2
.
The surface (top side in
FIG. 5B
) of the wiring conductor
2
and the back (bottom side in
FIG. 5B
) of the wiring conductor
2
exposed to the inside of via-hole
3
are plated with nickel (hereafter referred to as “Ni”) or gold (hereafter referred to as “Au”).
In a semiconductor mounting process, a semiconductor chip placed on solder resist
4
is connected to wiring conductor
2
by a wire bonding method using Au wire or the like, which is followed by resin molding. And, to connect a resin-molded package formed of the semiconductor chip and the circuit board to a board for mounting, a solder ball is heated and poured into via-hole
3
to make connection with conductor
2
.
Conventionally, in a case of an electro-plated film circuit board such as BGA, CSP, etc., Au/Ni 2-layer plating is performed in many cases. The top face of wiring conductor
2
including bonding area
5
and the back face of wiring conductor
2
exposed to the inside of via-hole
3
are plated in equal thickness with Ni and Au.
In this case, in Au plating of the top face of wiring conductor
2
, it is said that the thermal diffusion of surface Ni due to heating should be reduced and that Au plating should be thicker to obtain proper Au wire bonding (Fumiaki Iwakura): Surface-mounting technology, Vol. 7, No. 5, p. 60 (1997).
On the other hand, regarding the reliability of soldering, it is said that Au plating should be thinner, since brittle intermetallic compound of Au and Sn is formed thick and the solder ball strength decreases through lapse of time when the ratio of Au to Sn in the solder is increased exceeding a specific level (Nikkei Micro-Device, 2, 48, 1998).
And, a method of maintaining proper wire bonding ability by thinning Au layer to about 0.05 &mgr;m and removing the Ni diffused on the surface due to heating by plasma ashing in order to maintain the solder ball strength for a long period of time is proposed. Further, a method of 3-layer plating of Au, Pd and Ni have been proposed, but there still exist problems such as increased processing steps and complicated assembling steps.
Also, a method of thickening the Au plating to 0.2 &mgr;m in an attempt to satisfy both requirements for maintaining the solder ball strength for a long period of time and for obtaining proper wire bonding ability at the same time (Satoshi Chinda: Surface Technology, 49, 12, 1998) has been proposed. But, there still exists a fear of worsening of one of the above two characteristics irrespective of whether the Au plating is increased or decreased in thickness, and it is difficult to control the Au plating thickness.
The present invention is intended to provide a circuit board capable of satisfying the requirements for maintaining the solder ball strength for a long period of time and obtaining proper wire bonding ability at the same time, and a method of manufacturing same.
SUMMARY OF THE INVENTION
A circuit board of the present invention comprises an insulating substrate, via-holes made in the insulating substrate, and a wiring conductor having at least one layer disposed on the insulating substrate, and is characterized in that the gold-plated layer of the wiring conductor exposed to the inside of the via-hole is thinner than the gold-plated layer of the wiring conductor exposed to a portion other than the inside of the via-hole in the insulating substrate.
Also, a method of manufacturing a circuit board of the present invention comprises an insulating substrate and via-holes formed in the insulating substrate, and a wiring conductor having at least one layer disposed on the insulating substrate, wherein gold electroplating of the wiring conductor is performed with the open-side of the via-hole in the insulating substrate contacted on a shielding board in a plating bath, and a gold-plated layer of the wiring conductor exposed to the inside of the via-hole is formed thinner than a gold-plated layer of the wiring conductor exposed to a portion other than the inside of the via hole in the insulating substrate.
REFERENCES:
patent: 3616283 (1971-10-01), Magee et al.
patent: 4102772 (1978-07-01), Nakamura et al.
patent: 4186062 (1980-01-01), Eidschun
patent: 4230538 (1980-10-01), Turner
patent: 5176811 (1993-01-01), Keim et al.
patent: 5546655 (1996-08-01), Feger et al.
patent: 2000-183535 (2000-06-01), None
Iwakura, Fumiaki. “Reliability and Evaluation of Wire Bonding Circuit Board.”Surface-Mounting Technology, vol. 7, No. 5 (1977). pp. 60-63. Partial English translation.
Asakura, Hiroshi. “Structurally Improved CSP Clears Connection Reliability.”Nikkei Microdevices. Feb., 1998. pp. 48-55. Partial English translation.
Chinda, Akira, et al. “Influence of Nickel Plating Underlayer Deposition Conditions on Bending Characteristics of Palladium Plating Leadframe.”Surface Technology. vol. 49, No. 12 (1998). pp. 41-48. Partial English translation.
Mutschler Brian L.
Nguyen Nam
Parkhurst & Wendel L.L.P.
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