Fishing – trapping – and vermin destroying
Patent
1995-03-29
1996-06-18
Chaudhuri, Olik
Fishing, trapping, and vermin destroying
437919, 437245, H01L 2170, H01L 2700
Patent
active
055277292
ABSTRACT:
On a silicon substrate, a silicon oxide layer, a first platinum layer, a dielectric film and a second platinum layer are formed, and then the second platinum layer and the dielectric film are dry etched, via a resist layer, in a 1-5 Pa low pressure region with a mixed gas of HBr and O.sub.2 as the etching gas. As soon as the first platinum layer is exposed, the unetched portion of dielectric film is etched off in a 5-50 Pa high pressure region, and then the first platinum layer is dry etched again in the low pressure region to form a capacitor consisting of a top electrode, a capacitance insulation layer and a bottom electrode in a semiconductor integrated circuit chip. Using this manufacturing method prevents the deterioration in definition caused by the use of a thick resist and the operation failure of circuit elements such as transistors due to over etching on the insulation layer.
REFERENCES:
patent: 5173437 (1992-12-01), Chi
patent: 5286667 (1994-02-01), Lin et al.
patent: 5439840 (1995-08-01), Jones, Jr. et al.
Izutsu Yasufumi
Matsumoto Shoji
Nagano Yoshihisa
Shimada Yasuhiro
Chaudhuri Olik
Matsushita Electronics Corporation
Tsai H. Jey
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