Method of manufacturing a buried load device in an integrated ci

Details Method of manufacturing a buried load device in an integrated ci Method of manufacturing a buried load device in an integrated ci

1977-01-10

1978-09-26

Rutledge, L. Dewayne

Metal treatment

Process of modifying or maintaining internal physical...

Chemical-heat removing or burning of metal

29577C, 29580, 148 15, 148187, 357 20, 357 50, 357 51, 357 90, 357 52, H01L 2176, H01L 2936

Patent

active

041167325

ABSTRACT:
A buried load device in an integrated circuit extends between two regions of like conductivity isolated from each other by thick oxide and substrate comprises a channel beneath the oxide and having dimensions defined by a diffused region of opposite conductivity type. The buried channel is formed by impurity migration from an upper epitaxial layer that is oxidized to separate two regions and the connecting channel width is defined by diffused strip regions of opposite conductivity to establish a desired current-voltage relationship thereof.

REFERENCES:
patent: 3085033 (1963-04-01), Handelman
patent: 3203840 (1965-08-01), Harris
patent: 3386865 (1968-06-01), Duo
patent: 3418180 (1968-12-01), Ku
patent: 3489963 (1970-01-01), Gillett
patent: 3631313 (1971-12-01), Moore
patent: 3774088 (1973-11-01), Magdo et al.
patent: 3873372 (1975-03-01), Johnson
patent: 3873383 (1975-03-01), Kooi
patent: 3891469 (1975-06-01), Moriyama et al.
patent: 3928091 (1975-12-01), Tachi et al.
Deal et al., "Recent Advances . . . Metal-Oxide-Silicon System", Trans. Metall, Soc. Aime, vol. 233, Mar. 1965, pp. 524-529.

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