Semiconductor device manufacturing: process – Forming bipolar transistor by formation or alteration of...
Reexamination Certificate
1999-08-12
2001-04-17
Nguyen, Tuan H. (Department: 2813)
Semiconductor device manufacturing: process
Forming bipolar transistor by formation or alteration of...
C438S202000, C438S234000
Reexamination Certificate
active
06218253
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device and, more particularly, to a method of manufacturing a bipolar (BIP) transistor capable of being incorporated with complementary metal oxide semiconductor (CMOS) transistors on a single semiconductor substrate.
2. Description of the Related Art
A semiconductor device having a BIP transistor and CMOS transistors is called a BiCMOS device and presents excellent device characteristics by utilizing an advantage of low power consumption and high integration density of the CMOS transistors and a low noise and a high driving capacity of the BIP transistor. However, a device structure of the BiCMOS device and a manufacturing method of the same are relatively complicated, thereby requiring a relatively large chip area and deteriorating device characteristics.
This will be discussed in detail below with reference to
FIG. 2
illustrating a method of manufacturing a BiCMOS device according to the prior art as disclosed in, for example, “Subjects related to Process Integration for Submicron BICMOS Technique” (solid state technology/Japanese edition August
1992).
As shown in
FIG. 2A
, such a P-type silicon substrate
1
is prepared that has an nMOS section (a), a pMOS section (b), an isolation region section (c) and an BIP section (d). N
+
buried layers
2
are formed in the pMOS, section (b) and the BIP section (d), and P
+
buried layers
3
are formed in the nMOS section (a) and an isolation region section (c).
As shown in
FIG. 2B
, thereafter, an intrinsic epitaxial layer
4
is grown on the whole surfaces of the silicon substrate
1
, followed by selectively forming P-well regions
5
and N-well regions
6
in the layer
4
. The respective well regions
5
and
6
are formed in contact with corresponding ones of the burried regions
2
and
3
.
Selectively formed in the layer
4
are, as shown in FIG.
2
(C), field oxide films
7
in order to separate element regions by a selective thermal oxidation known as LOCOS (local oxidation of silicon) method. A P-type base layer
8
is then selectively formed in the well region
6
serving as a collector region. An N
+
type collector contact region layer
9
is thereafter formed so as to reach the N
+
buried layer
2
. Thereafter, a gate oxide film
10
is formed over an entire surface.
The gate oxide film
10
is covered with a polysilicon film
11
as shown in
FIG. 2D
, followed by an emitter opening
13
is selectively formed to expose a part of the base region
8
.
Another polysilicon film
12
is then deposited on the whole surface and N-type impurities are ion-implanted into the film
12
, followed by being patterned. As a result, as shown
FIG. 2F
, gate electrodes
14
A for nMOS and pMOS transistors and an emitter electorde
14
B for the BIP transistor are formed. Each of the electrodes
14
is composed of two polysilicon films
11
and
12
. Side walls
15
of silicon oxide film are thereafter formed on the respective sides of the gate electrodes
14
A and emitter electrode
14
B, and the oxide layer
10
is then selectively remove by using the electrodes
14
and the side walls
15
as a mask.
Thereafter, N-type impurities and P-type impurities are ion-implanted by using resist layers (not shown) as a mask, and heat treatment is performed to activate the implanted impurity ions. Consequently, N-type source and drain regions
16
, P-type source and drain region
17
and a graft base region
18
are formed, as shown in FIG.
2
F. At this time, the impurities contained in the polysilicon electrode
14
B are also diffused into the base layer
8
to form an N
+
-type emitter layer
19
. Silicide layers
20
are then formed on the respective surfaces of the regions
16
,
17
and
18
and the surfaces of the respective electrodes
14
A and
14
B to reduce electrical resistance.
Although not shown, interlayer insulating layers and wiring layer are thereafter formed to complete the device.
Thus, the BiCMOS device according to the prior art employs the buried regions
2
and
3
and the epitaxial layer
4
. Each of the buried regions
2
and
3
is formed at a high impurity concentration. Accordingly, each of the buried regions
2
and
3
expands in not only vertical direction but also horizontal direction, so that it reaches and contacts with the adjacent buried region. For this reason, large parasitic capacity is produced to thereby lower an operating speed. If the buried regions
2
and
3
would be formed separately from each other in order to eliminate the parasite capacity, the chip area would be inevitably increased and the integration density would be lowered.
During the epitaxial growth, moreover, the so-called out-diffusion occurs in which some of impurities contained each of the buried regions
2
and
3
are diffused outside and the controllability of the out-diffusion is very difficult, as well known in the art. For this reason, the impurity concentration of the epitaxial layer
4
is largely fractuated from the designed value to thereby change the threshold voltage control of each MOS transistor.
Further, in the prior art, a base layer is formed before a gate oxide film is formed, because contamination from a resist that is a mask for ion implanation to form a base layer exerts a bad influence upon the gate oxide film when the resist is applied directly to the gate oxide film. When oxidation is performed after ion implantation of the base, however, redistribution of a profile and suction of boron into an oxide film are produced, thus a shallow and sharp profile cannot be realized as a result. Since the performance of a BIP depends largely on the base profile, it is difficult to obtain high frequency characteristics by this method.
Against this problem, there is a method of performing base layer formation for a BIP, emitter opening, emitter polysilicon film formation, impurity ion implantation and patterning of emitter electrode after CMOS production process, in short, after patterning of gate electrode. However, there is such a drawback that the production process is further elongated when this technique is adopted. It has been +4 mask against a CMOS in the prior art, but +5 mask in this case.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a method of manufacturing a semiconductor device in which the above-mentioned problems of the conventional method are eliminated.
A method of manufacturing a semiconductor device having a bipolar transistor according to the present invention comprising the steps of: forming an emitter opening in an insulating film on the semiconductor substrate depositing a polysilicon film on the insulating film and in the emitter opening portion; implanting impurity ions into the substrate through the polysilicon film to form a collector layer and a base layer; and performing heat treatment, preferably lamp annealing at high temperature for a short length of time for activating impurities of the base layer and the collector layer, and diffusing impurities from the polysilicon into the semiconductor substrate to form an emitter diffused layer.
It is another feature of the present invention to provide a method of manufacturing a semiconductor device having the steps of: separating a first element region for providing a bipolar transistor and a second element region for providing a CMOS on a semiconductor substrate; forming an insulating film which becomes a gate insulating film in the second element region on the first and the second element regions forming an emitter opening in the insulating film of the-first element region; depositing a polysilicon film on the insulating film and in the emitter opening portion on the first and the second element regions; selectively implanting impurity ions into the semiconductor substrate of the first element region through the polysilicon film to form a collector layer and a base layer; and performing heat treatment, preferably lamp anneal treatment for a
NEC Corporation
Nguyen Tuan H.
Young & Thompson
LandOfFree
Method of manufacturing a bipolar transistor by using only... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of manufacturing a bipolar transistor by using only..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of manufacturing a bipolar transistor by using only... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2459727