Method of manufacturing a bipolar transistor

Details Method of manufacturing a bipolar transistor Method of manufacturing a bipolar transistor

1988-05-17

1991-10-08

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437158, 437909, 437979, 437984, 148DIG10, 148DIG11, 148DIG124, H01L 2126, H01L 21225

Patent

active

050554190

ABSTRACT:
A fully self-aligned polycrystalline silicon emitter bipolar transistor. Self-alignment of the p.sup.+ base contact (12) is achieved by using oxidized sidewalls (8) (sidewall spacers) of the emitter mesa (7) as part of the p.sup.+ base contact implantation mask. Collector contact (13) alignment can be achieved using oxidized sidewalls (17) of polycrystalline silicon alignment mesas (14) defined in the same polysilicon as the emitter mesa (7) but deposited on oxide (2) rather than the implanted base region (5).

REFERENCES:
patent: 4188707 (1980-02-01), Asano et al.
patent: 4377903 (1983-03-01), Kanzaki et al.
patent: 4407059 (1983-10-01), Sasaki
patent: 4745080 (1988-05-01), Scovell et al.
Cuthbertson et al., "Self-Aligned Transistors with Polysilicon Emitters for Bipolar VLSI", IEEE, vol. ED 32, No. 2, 2/85, pp. 242-247.

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